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JPS5794857A - Logic device - Google Patents

Logic device

Info

Publication number
JPS5794857A
JPS5794857A JP55170834A JP17083480A JPS5794857A JP S5794857 A JPS5794857 A JP S5794857A JP 55170834 A JP55170834 A JP 55170834A JP 17083480 A JP17083480 A JP 17083480A JP S5794857 A JPS5794857 A JP S5794857A
Authority
JP
Japan
Prior art keywords
flip
diagnosis
flops
flop
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55170834A
Other languages
Japanese (ja)
Other versions
JPS6125173B2 (en
Inventor
Shigeaki Morisawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55170834A priority Critical patent/JPS5794857A/en
Publication of JPS5794857A publication Critical patent/JPS5794857A/en
Publication of JPS6125173B2 publication Critical patent/JPS6125173B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To increase the efficiency of diagnosis, by securing a free selection of a shift bus in accordance with the purpose of use and accordingly reducing the time of diagnosis as well as facilitating an easy control of a diagnosis program. CONSTITUTION:For the data for observation of a scratch pad memory, O and the addresses are supplied to a flip-flop 400 and flip-flops 401-403 respectively based on the setting method of the flip-flop and in the state under which ''1'' is applied to a terminal 493. Then the contents of the scratch pad memory is read to flip-flops 430-433 by applying a clock signal 481 by a step. Thus O is applied to the terminal 493 to observe the flip-flops 430-433 based on a flip-flop observing method. In this case, only the data of the memory is transferred to a diagnosing device 2 to ensure a highly efficient diagnosis.
JP55170834A 1980-12-05 1980-12-05 Logic device Granted JPS5794857A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55170834A JPS5794857A (en) 1980-12-05 1980-12-05 Logic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55170834A JPS5794857A (en) 1980-12-05 1980-12-05 Logic device

Publications (2)

Publication Number Publication Date
JPS5794857A true JPS5794857A (en) 1982-06-12
JPS6125173B2 JPS6125173B2 (en) 1986-06-14

Family

ID=15912190

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55170834A Granted JPS5794857A (en) 1980-12-05 1980-12-05 Logic device

Country Status (1)

Country Link
JP (1) JPS5794857A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015569A (en) * 1983-07-08 1985-01-26 Hitachi Ltd Logical package diagnostic system
JPH0368038A (en) * 1989-08-08 1991-03-25 Nec Eng Ltd Information processor
JPH03244039A (en) * 1990-02-22 1991-10-30 Nec Corp Fault information collecting system for information processor
JPH08226953A (en) * 1993-04-05 1996-09-03 Hitachi Ltd Logical package diagnosis method
US6611934B2 (en) 1988-09-07 2003-08-26 Texas Instruments Incorporated Boundary scan test cell circuit
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6763485B2 (en) 1998-02-25 2004-07-13 Texas Instruments Incorporated Position independent testing of circuits
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US6959408B2 (en) 1989-06-30 2005-10-25 Texas Instruments Incorporated IC with serial scan path, protocol memory, and event circuit
US6975980B2 (en) 1998-02-18 2005-12-13 Texas Instruments Incorporated Hierarchical linking module connection to access ports of embedded cores
US7058862B2 (en) 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015569A (en) * 1983-07-08 1985-01-26 Hitachi Ltd Logical package diagnostic system
US6813738B2 (en) 1988-09-07 2004-11-02 Texas Instruments Incorporated IC test cell with memory output connected to input multiplexer
US6611934B2 (en) 1988-09-07 2003-08-26 Texas Instruments Incorporated Boundary scan test cell circuit
US6898544B2 (en) 1988-09-07 2005-05-24 Texas Instruments Incorporated Instruction register and access port gated clock for scan cells
US7058871B2 (en) 1989-06-30 2006-06-06 Texas Instruments Incorporated Circuit with expected data memory coupled to serial input lead
US6996761B2 (en) 1989-06-30 2006-02-07 Texas Instruments Incorporated IC with protocol selection memory coupled to serial scan path
US6990620B2 (en) 1989-06-30 2006-01-24 Texas Instruments Incorporated Scanning a protocol signal into an IC for performing a circuit operation
US6959408B2 (en) 1989-06-30 2005-10-25 Texas Instruments Incorporated IC with serial scan path, protocol memory, and event circuit
JPH0368038A (en) * 1989-08-08 1991-03-25 Nec Eng Ltd Information processor
JPH03244039A (en) * 1990-02-22 1991-10-30 Nec Corp Fault information collecting system for information processor
JPH08226953A (en) * 1993-04-05 1996-09-03 Hitachi Ltd Logical package diagnosis method
US6975980B2 (en) 1998-02-18 2005-12-13 Texas Instruments Incorporated Hierarchical linking module connection to access ports of embedded cores
US6763485B2 (en) 1998-02-25 2004-07-13 Texas Instruments Incorporated Position independent testing of circuits
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US7058862B2 (en) 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state

Also Published As

Publication number Publication date
JPS6125173B2 (en) 1986-06-14

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