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JPS554683A - Test device for logic circuit - Google Patents

Test device for logic circuit

Info

Publication number
JPS554683A
JPS554683A JP7840278A JP7840278A JPS554683A JP S554683 A JPS554683 A JP S554683A JP 7840278 A JP7840278 A JP 7840278A JP 7840278 A JP7840278 A JP 7840278A JP S554683 A JPS554683 A JP S554683A
Authority
JP
Japan
Prior art keywords
register
file
logic circuit
test
test data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7840278A
Other languages
Japanese (ja)
Other versions
JPS612218B2 (en
Inventor
Hideo Morisue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7840278A priority Critical patent/JPS554683A/en
Publication of JPS554683A publication Critical patent/JPS554683A/en
Publication of JPS612218B2 publication Critical patent/JPS612218B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To ensure an easy test for the logic circuit including the register file by writing the test data delivered from the combination circuit into the specified register of the register file and then comparing the shift-out output value with the correct value.
CONSTITUTION: Register file 2 consists of plural units of the shift register and stores the test data into the specified register for the test of the logic circuit. The test data given from file 2 is read out and then applied to combination circuit 3 along with the output of register 1. Then the test data delivered from circuit 3 is written into the specified register in file 2, and the output value shifted out of shift data output line 14 is compared with the correct value. Thus, an easy test can be secured for the logic circuit including the register file.
COPYRIGHT: (C)1980,JPO&Japio
JP7840278A 1978-06-27 1978-06-27 Test device for logic circuit Granted JPS554683A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7840278A JPS554683A (en) 1978-06-27 1978-06-27 Test device for logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7840278A JPS554683A (en) 1978-06-27 1978-06-27 Test device for logic circuit

Publications (2)

Publication Number Publication Date
JPS554683A true JPS554683A (en) 1980-01-14
JPS612218B2 JPS612218B2 (en) 1986-01-23

Family

ID=13661022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7840278A Granted JPS554683A (en) 1978-06-27 1978-06-27 Test device for logic circuit

Country Status (1)

Country Link
JP (1) JPS554683A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63191151U (en) * 1988-04-25 1988-12-09

Also Published As

Publication number Publication date
JPS612218B2 (en) 1986-01-23

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