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JPS554684A - Test device for logic circuit - Google Patents

Test device for logic circuit

Info

Publication number
JPS554684A
JPS554684A JP7840378A JP7840378A JPS554684A JP S554684 A JPS554684 A JP S554684A JP 7840378 A JP7840378 A JP 7840378A JP 7840378 A JP7840378 A JP 7840378A JP S554684 A JPS554684 A JP S554684A
Authority
JP
Japan
Prior art keywords
file
register
test
logic circuit
given
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7840378A
Other languages
Japanese (ja)
Other versions
JPS612219B2 (en
Inventor
Hideo Morisue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7840378A priority Critical patent/JPS554684A/en
Publication of JPS554684A publication Critical patent/JPS554684A/en
Publication of JPS612219B2 publication Critical patent/JPS612219B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To ensure an easy test for the logic circuit including the register file by writing the test result given from the combination circuit into all registers of the register file at one time and then comparing the output value with the correct value.
CONSTITUTION: Register file 2 consists of plural units of the shift register and stores the test data into the registers at one time for the test of the logic circuit. And the data given from file 2 is given to combination circuit 3 along with the output of register 1. Then the test result given from circuit 3 is written into all registers of file 2 at one time, and the value of register 1 and file 2 delivered from shift data output line 14 is compared with the correct value. As a result, the test can be given easily to the logic circuit including the register file.
COPYRIGHT: (C)1980,JPO&Japio
JP7840378A 1978-06-27 1978-06-27 Test device for logic circuit Granted JPS554684A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7840378A JPS554684A (en) 1978-06-27 1978-06-27 Test device for logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7840378A JPS554684A (en) 1978-06-27 1978-06-27 Test device for logic circuit

Publications (2)

Publication Number Publication Date
JPS554684A true JPS554684A (en) 1980-01-14
JPS612219B2 JPS612219B2 (en) 1986-01-23

Family

ID=13661052

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7840378A Granted JPS554684A (en) 1978-06-27 1978-06-27 Test device for logic circuit

Country Status (1)

Country Link
JP (1) JPS554684A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56103529A (en) * 1980-01-22 1981-08-18 Fujitsu Ltd Flip-flop circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56103529A (en) * 1980-01-22 1981-08-18 Fujitsu Ltd Flip-flop circuit
JPH0342013B2 (en) * 1980-01-22 1991-06-25

Also Published As

Publication number Publication date
JPS612219B2 (en) 1986-01-23

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