JPS5786969A - Doubled computer system - Google Patents
Doubled computer systemInfo
- Publication number
- JPS5786969A JPS5786969A JP55163045A JP16304580A JPS5786969A JP S5786969 A JPS5786969 A JP S5786969A JP 55163045 A JP55163045 A JP 55163045A JP 16304580 A JP16304580 A JP 16304580A JP S5786969 A JPS5786969 A JP S5786969A
- Authority
- JP
- Japan
- Prior art keywords
- controller
- cpus
- input
- signal
- output bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:To prevent a system from being shut down by supplying a permit signal for the use of an input-output bus from a doubling controller to two CPUs selectively even through manual operation, and by preventing the signals from being established simultaneously in only one abnormal event. CONSTITUTION:The input-output buses 51 and 52 of CPUs 1 and 2 are connected to a common input-output bus 53 on wired OR basis to supply a permit signal for the use of the input-output bus to two CPUs selectively from a doubling controller 3 through a simultaneous active interlocking circuit. This signal is also obtained by operating switches 41 and 42 manually and if the controller 3 becomes abnormal, the said permit signal is secured through manual operation to repair the controller 3 during the period. Further, the original control signal of the controller 3, a control signal supplied actually to both the CPUs, and closure state signals of the switches 41 and 42 are used in combination in the controller 3 to discriminate and display whether the control signals are normal or abnormal, thus preventing a system from being shut down unless two faults overlap each other at the output terminal of the controller 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55163045A JPS5786969A (en) | 1980-11-19 | 1980-11-19 | Doubled computer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55163045A JPS5786969A (en) | 1980-11-19 | 1980-11-19 | Doubled computer system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5786969A true JPS5786969A (en) | 1982-05-31 |
| JPS61663B2 JPS61663B2 (en) | 1986-01-10 |
Family
ID=15766126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55163045A Granted JPS5786969A (en) | 1980-11-19 | 1980-11-19 | Doubled computer system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5786969A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007326593A (en) * | 2006-06-06 | 2007-12-20 | Cp Toms:Kk | Container |
-
1980
- 1980-11-19 JP JP55163045A patent/JPS5786969A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007326593A (en) * | 2006-06-06 | 2007-12-20 | Cp Toms:Kk | Container |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61663B2 (en) | 1986-01-10 |
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