JPS5786951A - Information processor - Google Patents
Information processorInfo
- Publication number
- JPS5786951A JPS5786951A JP16380180A JP16380180A JPS5786951A JP S5786951 A JPS5786951 A JP S5786951A JP 16380180 A JP16380180 A JP 16380180A JP 16380180 A JP16380180 A JP 16380180A JP S5786951 A JPS5786951 A JP S5786951A
- Authority
- JP
- Japan
- Prior art keywords
- address
- bit
- microinstruction
- circuit
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/261—Microinstruction address formation
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To perform efficient address assignment by providing a circuit which modifies one bit or bits of a constant part and a circuit which controls which bit of the constant part is to be modified. CONSTITUTION:A microinstruction 101 read out of a microinstruction storage part 4 is held in a microinstruction holding register 1. An instruction code 102 in the register 1 is supplied to a decoding circuit 3 and when a constant is not used as an address, a modification indication signal 103 which has logic 1 is generated. A constat modifying circuit 2 inverts an address bit 104 to output it as an address bit 105 when the signal 103 has the logic 1 or outputs the address bit 104 as it is as the address bit 105 when the signal 103 has logic 0. Then, address bits 105, 106 and 107 are sent as an address 108 to a microinstruction address register 5 to read the next microinstruction out of the circuit 4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16380180A JPS5786951A (en) | 1980-11-20 | 1980-11-20 | Information processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16380180A JPS5786951A (en) | 1980-11-20 | 1980-11-20 | Information processor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5786951A true JPS5786951A (en) | 1982-05-31 |
JPS6223890B2 JPS6223890B2 (en) | 1987-05-26 |
Family
ID=15780953
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16380180A Granted JPS5786951A (en) | 1980-11-20 | 1980-11-20 | Information processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5786951A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5350634A (en) * | 1976-10-18 | 1978-05-09 | Honeywell Inf Systems | Microprogram address double forming device |
JPS5398752A (en) * | 1977-02-10 | 1978-08-29 | Hitachi Ltd | Microprogram control system |
-
1980
- 1980-11-20 JP JP16380180A patent/JPS5786951A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5350634A (en) * | 1976-10-18 | 1978-05-09 | Honeywell Inf Systems | Microprogram address double forming device |
JPS5398752A (en) * | 1977-02-10 | 1978-08-29 | Hitachi Ltd | Microprogram control system |
Also Published As
Publication number | Publication date |
---|---|
JPS6223890B2 (en) | 1987-05-26 |
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