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JPS57754A - Arithemtic processing system - Google Patents

Arithemtic processing system

Info

Publication number
JPS57754A
JPS57754A JP7397380A JP7397380A JPS57754A JP S57754 A JPS57754 A JP S57754A JP 7397380 A JP7397380 A JP 7397380A JP 7397380 A JP7397380 A JP 7397380A JP S57754 A JPS57754 A JP S57754A
Authority
JP
Japan
Prior art keywords
arithmetic processing
prescribed
rom1
during
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7397380A
Other languages
Japanese (ja)
Inventor
Yoshinobu Muranaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP7397380A priority Critical patent/JPS57754A/en
Publication of JPS57754A publication Critical patent/JPS57754A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To speed arithmetic processing by executing different prescribed arithmetic processing during the period of access to an ROM, by utilizing a prescribed timing signal from a timing signal generating means.
CONSTITUTION: In a system which performs arithmetic processing by controlling operation to a random access memory RAM3 by a control program in an ROM1, prescribed timing signals CW2 and CW2' generated during the period of access to the ROM1 in the prescribed arithmetic processing of the ROM1 are utilized to control the output of a microinstruction CO, and during clocking processing, numeric code data 1 for time addition is supplied to an arithmetic circuit 4. Thus, parallel arithmetic processing is performed.
COPYRIGHT: (C)1982,JPO&Japio
JP7397380A 1980-06-02 1980-06-02 Arithemtic processing system Pending JPS57754A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7397380A JPS57754A (en) 1980-06-02 1980-06-02 Arithemtic processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7397380A JPS57754A (en) 1980-06-02 1980-06-02 Arithemtic processing system

Publications (1)

Publication Number Publication Date
JPS57754A true JPS57754A (en) 1982-01-05

Family

ID=13533532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7397380A Pending JPS57754A (en) 1980-06-02 1980-06-02 Arithemtic processing system

Country Status (1)

Country Link
JP (1) JPS57754A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0264878B1 (en) * 1986-10-20 1991-04-03 Mitsubishi Kasei Corporation Water-soluble disazo colorants

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49107644A (en) * 1973-02-19 1974-10-12
JPS5099652A (en) * 1973-12-29 1975-08-07
JPS5369557A (en) * 1976-12-03 1978-06-21 Fujitsu Ltd Data processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49107644A (en) * 1973-02-19 1974-10-12
JPS5099652A (en) * 1973-12-29 1975-08-07
JPS5369557A (en) * 1976-12-03 1978-06-21 Fujitsu Ltd Data processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0264878B1 (en) * 1986-10-20 1991-04-03 Mitsubishi Kasei Corporation Water-soluble disazo colorants

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