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JPS553011A - Error processing system for sequence control unit - Google Patents

Error processing system for sequence control unit

Info

Publication number
JPS553011A
JPS553011A JP7422478A JP7422478A JPS553011A JP S553011 A JPS553011 A JP S553011A JP 7422478 A JP7422478 A JP 7422478A JP 7422478 A JP7422478 A JP 7422478A JP S553011 A JPS553011 A JP S553011A
Authority
JP
Japan
Prior art keywords
error processing
jump
memory
given
case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7422478A
Other languages
Japanese (ja)
Inventor
Masami Yuki
Isao Yasuda
Juntaro Kamei
Kazuyoshi Asada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7422478A priority Critical patent/JPS553011A/en
Publication of JPS553011A publication Critical patent/JPS553011A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE: To perform the error processing with a simple constitution by delivering the special order pattern from CPU and then giving jump to the head address of the error process program in case a misjump is given to the area where no memory is packaged.
CONSTITUTION: The CPU operates based on the sequence program read out. In this case, if a jump is given to the area where no memory is packaged and CPU gives start signal SRVI to the memory nonpackaged address, the time when the answer signal returns is monitored by time-out detection counter 23. And in case, no answer signal returns within a fixed time, the misjump is identified and then the special order pattern set at setting circuit 38 is delivered to bus 10. Thus, a jump is given to the head address of the error process program to carry out the error processing.
COPYRIGHT: (C)1980,JPO&Japio
JP7422478A 1978-06-21 1978-06-21 Error processing system for sequence control unit Pending JPS553011A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7422478A JPS553011A (en) 1978-06-21 1978-06-21 Error processing system for sequence control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7422478A JPS553011A (en) 1978-06-21 1978-06-21 Error processing system for sequence control unit

Publications (1)

Publication Number Publication Date
JPS553011A true JPS553011A (en) 1980-01-10

Family

ID=13540989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7422478A Pending JPS553011A (en) 1978-06-21 1978-06-21 Error processing system for sequence control unit

Country Status (1)

Country Link
JP (1) JPS553011A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5760408A (en) * 1980-09-30 1982-04-12 Okuma Mach Works Ltd Numerical control system capable of controlling external interruption
JPS6083149A (en) * 1983-10-13 1985-05-11 Nec Corp Computer
JPH04107745A (en) * 1990-08-29 1992-04-09 Nec Ic Microcomput Syst Ltd In-circuit emulator

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5760408A (en) * 1980-09-30 1982-04-12 Okuma Mach Works Ltd Numerical control system capable of controlling external interruption
JPS6083149A (en) * 1983-10-13 1985-05-11 Nec Corp Computer
JPH04107745A (en) * 1990-08-29 1992-04-09 Nec Ic Microcomput Syst Ltd In-circuit emulator

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