JPS5754451A - Phase locked loop circuit for digital communication - Google Patents
Phase locked loop circuit for digital communicationInfo
- Publication number
- JPS5754451A JPS5754451A JP55128599A JP12859980A JPS5754451A JP S5754451 A JPS5754451 A JP S5754451A JP 55128599 A JP55128599 A JP 55128599A JP 12859980 A JP12859980 A JP 12859980A JP S5754451 A JPS5754451 A JP S5754451A
- Authority
- JP
- Japan
- Prior art keywords
- bit synchronizing
- phase
- input terminal
- digital information
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 abstract 1
- 238000005070 sampling Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To obtain stable internal bit synchronizing signal, by controlling the phase of a bit synchronizing signal of digital information transmitted from a transmission side and of an internal bit synchronizing signal at reception side and taking synchronism for both bit synchronizing signals. CONSTITUTION:Digital information at an input terminal 1 is applied to a wave shape circit 3 to detect edges of leading and trailing of the input digital information, and picked up bit synchronizing pulses are generated and they are applied to one input terminal of a phase comparator 4. An output pulse of a voltage controlled oscillator VCO is applied to another input terminal of the comparator 4, the circuit 4 detects the phase difference and an analog signal corresponding to the phase difference is outputted. This output is applied to a sample hold curcuit 6, and a sample hold circuit is provided at the post stage of the circuit 6, and the operation of both circuits 6, 7 are controlled with a sampling timing controller 8. Thus, the effect of phase signal caused by missing bit synchronizing pulse can be rejected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55128599A JPS5754451A (en) | 1980-09-18 | 1980-09-18 | Phase locked loop circuit for digital communication |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55128599A JPS5754451A (en) | 1980-09-18 | 1980-09-18 | Phase locked loop circuit for digital communication |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5754451A true JPS5754451A (en) | 1982-03-31 |
Family
ID=14988750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55128599A Pending JPS5754451A (en) | 1980-09-18 | 1980-09-18 | Phase locked loop circuit for digital communication |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5754451A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61166239A (en) * | 1985-01-18 | 1986-07-26 | Oki Electric Ind Co Ltd | Timing recovery circuit |
| JPS63318848A (en) * | 1987-06-22 | 1988-12-27 | Furuno Electric Co Ltd | Synchronizing signal generating circuit device |
-
1980
- 1980-09-18 JP JP55128599A patent/JPS5754451A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61166239A (en) * | 1985-01-18 | 1986-07-26 | Oki Electric Ind Co Ltd | Timing recovery circuit |
| JPS63318848A (en) * | 1987-06-22 | 1988-12-27 | Furuno Electric Co Ltd | Synchronizing signal generating circuit device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0360691A3 (en) | Apparatus for receiving digital signal | |
| JPS5754451A (en) | Phase locked loop circuit for digital communication | |
| JPS5686582A (en) | Quantizing system at reception side for video information transmitter | |
| JPS5619263A (en) | Waveform shaping circuit | |
| JPS57105016A (en) | Clock source switching system | |
| GB1049916A (en) | Method for synchronizing electrical circuits | |
| GB977474A (en) | Tone frequency control means for keyed filtered systems | |
| JPS56169974A (en) | Receiver for multiplex information signal | |
| JPS5634267A (en) | Synchronizing circuit | |
| JPS54141507A (en) | Phase synchronism circuit | |
| JPS564938A (en) | Phase synchronizing circuit | |
| JPS5620355A (en) | Clock signal forming circuit | |
| JPS6442949A (en) | Timing extraction circuit | |
| JPS5430060A (en) | Dislocation detecting circuit | |
| JPS6412691A (en) | Video signal sampling circuit | |
| JPS57162526A (en) | Phase synchronizing circuit | |
| JPS6033650Y2 (en) | Synchronous signal separation device | |
| JPS5547774A (en) | Phase synchronism circuit | |
| GB1520290A (en) | Phase acquisition | |
| JPS5684081A (en) | Still picture receiver | |
| SU1525930A1 (en) | Device for receiving relative bi-pulse signal | |
| JPS6444194A (en) | Sampling clock generator for video signal | |
| SU1293848A1 (en) | Clock synchronization device for nrz-l signal receiver | |
| JPS6436142A (en) | Bit phase synchronizing circuit | |
| JPS5599864A (en) | Absorbing unit for timing fluctuation |