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JPS5746395A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS5746395A
JPS5746395A JP12324480A JP12324480A JPS5746395A JP S5746395 A JPS5746395 A JP S5746395A JP 12324480 A JP12324480 A JP 12324480A JP 12324480 A JP12324480 A JP 12324480A JP S5746395 A JPS5746395 A JP S5746395A
Authority
JP
Japan
Prior art keywords
fixed
decoder
level
circuit
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12324480A
Other languages
Japanese (ja)
Other versions
JPS6233768B2 (en
Inventor
Makoto Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12324480A priority Critical patent/JPS5746395A/en
Publication of JPS5746395A publication Critical patent/JPS5746395A/en
Publication of JPS6233768B2 publication Critical patent/JPS6233768B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Landscapes

  • Read Only Memory (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To avoid the leakage of write information, by installing a circuit to inactivate a writing decoder. CONSTITUTION:The junction between the emitter and the base of a writing point 24 is once destroyed to make the state of conduction, then the input of a buffer 27 is fixed at L level. Accordingly a preventing circuit control signal 26 is fixed at L level, and the outputs are fixed to decoder control preventing circuits 21, 22 and 23 to interrupt supply of signals to decoder control signals 1, 15 and 12 respectively. Thus the decoders are all inactivated. In other words, the state of a write information leakage preventing circuit is working is realized.
JP12324480A 1980-09-05 1980-09-05 Integrated circuit Granted JPS5746395A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12324480A JPS5746395A (en) 1980-09-05 1980-09-05 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12324480A JPS5746395A (en) 1980-09-05 1980-09-05 Integrated circuit

Publications (2)

Publication Number Publication Date
JPS5746395A true JPS5746395A (en) 1982-03-16
JPS6233768B2 JPS6233768B2 (en) 1987-07-22

Family

ID=14855766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12324480A Granted JPS5746395A (en) 1980-09-05 1980-09-05 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS5746395A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61134997A (en) * 1984-12-04 1986-06-23 Nec Corp Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61134997A (en) * 1984-12-04 1986-06-23 Nec Corp Semiconductor integrated circuit

Also Published As

Publication number Publication date
JPS6233768B2 (en) 1987-07-22

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