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JPS5737827A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5737827A
JPS5737827A JP11343580A JP11343580A JPS5737827A JP S5737827 A JPS5737827 A JP S5737827A JP 11343580 A JP11343580 A JP 11343580A JP 11343580 A JP11343580 A JP 11343580A JP S5737827 A JPS5737827 A JP S5737827A
Authority
JP
Japan
Prior art keywords
layer
injected
face direction
epitaxial layer
whereon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11343580A
Other languages
Japanese (ja)
Inventor
Eiji Murata
Mitsugi Higashiura
Hiroshi Ishimura
Hisao Kamo
Takashi Udagawa
Tokuji Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11343580A priority Critical patent/JPS5737827A/en
Publication of JPS5737827A publication Critical patent/JPS5737827A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To reduce the variation of the carrier density of the epitaxial layer for the subject semiconductor device by a method wherein impurities are injected in an n type GaAs epitaxial layer and a substrate, having the face direction deflected from a face direction (100), is used for the device with which an annealing process is performed in the atmosphere containing arsine. CONSTITUTION:For example, on the n type layer whereon an n<++> type GaAs crystal 11 has been epitaxially grown, Si is injected, for example, an annealing is performed on the above layer 12 in the hydrogeneous atomosphere having an arsine partial pressure of 0.01-10torr at the temperature of 500-950 deg.C and a superstepped junction is formed, for example, by having the injected layer 14 activated to an n<+> layer 14. On this GaAs substrate 13, the crystal having the deflection of 5-15 degrees from the surface (100), whereon a face direction is normally in use, is used. Through these procedures, almost no variation in carrier density of the epitaxial layer in the annealing process is generated and this enables to produce good effects on both the characteristics of the element and the manufacture thereof.
JP11343580A 1980-08-20 1980-08-20 Manufacture of semiconductor device Pending JPS5737827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11343580A JPS5737827A (en) 1980-08-20 1980-08-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11343580A JPS5737827A (en) 1980-08-20 1980-08-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5737827A true JPS5737827A (en) 1982-03-02

Family

ID=14612141

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11343580A Pending JPS5737827A (en) 1980-08-20 1980-08-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5737827A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814284A (en) * 1986-10-27 1989-03-21 Kabushiki Kaisha Toshiba GaAs plannar diode and manufacturing method therefor
US9764873B2 (en) 2005-10-14 2017-09-19 Graham Packaging Company, L.P. Repositionable base structure for a container
US9994378B2 (en) 2011-08-15 2018-06-12 Graham Packaging Company, L.P. Plastic containers, base configurations for plastic containers, and systems, methods, and base molds thereof
US10035690B2 (en) 2009-01-06 2018-07-31 Graham Packaging Company, L.P. Deformable container with hoop rings
US10118331B2 (en) 2006-04-07 2018-11-06 Graham Packaging Company, L.P. System and method for forming a container having a grip region
US10189596B2 (en) 2011-08-15 2019-01-29 Graham Packaging Company, L.P. Plastic containers having base configurations with up-stand walls having a plurality of rings, and systems, methods, and base molds thereof
US10501225B2 (en) 2003-07-30 2019-12-10 Graham Packaging Company, L.P. Container handling system

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814284A (en) * 1986-10-27 1989-03-21 Kabushiki Kaisha Toshiba GaAs plannar diode and manufacturing method therefor
US10501225B2 (en) 2003-07-30 2019-12-10 Graham Packaging Company, L.P. Container handling system
US9764873B2 (en) 2005-10-14 2017-09-19 Graham Packaging Company, L.P. Repositionable base structure for a container
US10118331B2 (en) 2006-04-07 2018-11-06 Graham Packaging Company, L.P. System and method for forming a container having a grip region
US10035690B2 (en) 2009-01-06 2018-07-31 Graham Packaging Company, L.P. Deformable container with hoop rings
US9994378B2 (en) 2011-08-15 2018-06-12 Graham Packaging Company, L.P. Plastic containers, base configurations for plastic containers, and systems, methods, and base molds thereof
US10189596B2 (en) 2011-08-15 2019-01-29 Graham Packaging Company, L.P. Plastic containers having base configurations with up-stand walls having a plurality of rings, and systems, methods, and base molds thereof

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