JPS5725003A - Pulse width controller - Google Patents
Pulse width controllerInfo
- Publication number
- JPS5725003A JPS5725003A JP10103680A JP10103680A JPS5725003A JP S5725003 A JPS5725003 A JP S5725003A JP 10103680 A JP10103680 A JP 10103680A JP 10103680 A JP10103680 A JP 10103680A JP S5725003 A JPS5725003 A JP S5725003A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- pulse width
- operator
- switch
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B11/00—Automatic controllers
- G05B11/01—Automatic controllers electric
- G05B11/26—Automatic controllers electric in which the output signal is a pulse-train
- G05B11/28—Automatic controllers electric in which the output signal is a pulse-train using pulse-height modulation; using pulse-width modulation
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Feedback Control In General (AREA)
Abstract
PURPOSE:To execute a control with high accuracy, by determining the hysteresis width of a comparator by the sum of a control deviation and a signal for setting a minimum pulse width output value, and securing th minimum pulse width even when a control signal is zero. CONSTITUTION:When an output signal E0 is off, to an operator 5 is provided an output signal of an operator 4 through a switch SW1, and to an adder 6 are provided an output Ei of the operator 5, also a control signal Ee through a switch SW2, and a minimum pulse width signal Ep through a switch SW3. Off of the signal E0 is continued until the signal Ei exceeds the sum of the signal Ee and the signal Ep. On the other hand, when the signal Ei exceeds the sum of the signal Ee and the signal Ep, the signal E0 of a comparator 7 becomes on, and to the operator is provided the signal E0 through a feeding-back circuit 9 and the switch SW1. To the adder 6 is provided the signal Ei, but common contacts C of the switches SW2, SW3 are connected to common potential points, respectively, and on of the signal E0 is continued until the signal Ei becomes zero.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10103680A JPS5725003A (en) | 1980-07-23 | 1980-07-23 | Pulse width controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10103680A JPS5725003A (en) | 1980-07-23 | 1980-07-23 | Pulse width controller |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5725003A true JPS5725003A (en) | 1982-02-09 |
JPS6150321B2 JPS6150321B2 (en) | 1986-11-04 |
Family
ID=14289931
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10103680A Granted JPS5725003A (en) | 1980-07-23 | 1980-07-23 | Pulse width controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5725003A (en) |
-
1980
- 1980-07-23 JP JP10103680A patent/JPS5725003A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6150321B2 (en) | 1986-11-04 |
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