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JPS5617472A - Arithmetic unit - Google Patents

Arithmetic unit

Info

Publication number
JPS5617472A
JPS5617472A JP9397479A JP9397479A JPS5617472A JP S5617472 A JPS5617472 A JP S5617472A JP 9397479 A JP9397479 A JP 9397479A JP 9397479 A JP9397479 A JP 9397479A JP S5617472 A JPS5617472 A JP S5617472A
Authority
JP
Japan
Prior art keywords
input
integrator
signal
output
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9397479A
Other languages
Japanese (ja)
Inventor
Fumio Sugiyama
Isao Tashiro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9397479A priority Critical patent/JPS5617472A/en
Publication of JPS5617472A publication Critical patent/JPS5617472A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To improve multiplication precision remarkably with a simple constitution by shifting the 2nd input signal in phase from the 1st input signal by a fixed value. CONSTITUTION:The 1st input signal Vi1 is input to integrator 2 by way of switch 1a. Reference signals Vr and -Vr are also input to integrator 2 selectively through switches 1b and 1c. The output of integrator 2 is input to comparator 3. This comparator 3, when the output of integrator 2 is greater than a comparison reference level, generates a signal of level H, which is supplied to switch control circuit 4 to perform pulse-width modulation that corresponds to signal Vi1. Input signal Vr2, on the other hand, is phase-delayed through phase circuit 6 and then input to integrator 7 through switch 5 turned on-off with the output of circuit 4. This integra- tor 7 outputs the products of signals Vr1 and Vr2. Thus, signal Vr2 is delayed by a certain time width to eliminate equivalently sampling time difference from signals Vr1 and Vr2, so that a high-precision arithmetic value can be obtained.
JP9397479A 1979-07-24 1979-07-24 Arithmetic unit Pending JPS5617472A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9397479A JPS5617472A (en) 1979-07-24 1979-07-24 Arithmetic unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9397479A JPS5617472A (en) 1979-07-24 1979-07-24 Arithmetic unit

Publications (1)

Publication Number Publication Date
JPS5617472A true JPS5617472A (en) 1981-02-19

Family

ID=14097366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9397479A Pending JPS5617472A (en) 1979-07-24 1979-07-24 Arithmetic unit

Country Status (1)

Country Link
JP (1) JPS5617472A (en)

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