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JPS5723243A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS5723243A
JPS5723243A JP9772580A JP9772580A JPS5723243A JP S5723243 A JPS5723243 A JP S5723243A JP 9772580 A JP9772580 A JP 9772580A JP 9772580 A JP9772580 A JP 9772580A JP S5723243 A JPS5723243 A JP S5723243A
Authority
JP
Japan
Prior art keywords
layer
fet
wiring
capacitive
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9772580A
Other languages
Japanese (ja)
Inventor
Juri Kato
Yasutaka Nakasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP9772580A priority Critical patent/JPS5723243A/en
Publication of JPS5723243A publication Critical patent/JPS5723243A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To enable simultaneous forming of a circuit constitutional elements in MOSIC by providing a method wherein an ion implantation layer is formed in a region separated by selective oxidation through a gate film to form D type FET to which applied is a capacitive or crossing wiring. CONSTITUTION:In the case of CMOSIC, P type impurities 6 are applied into a substrate 4 with a selectively oxidized layer 1, P well 2 and a gate membrane 3 being formed on it, with a resist 5 as a mask. N type impurities implantation region is provided in the P well 2. The amount of each ion implantation is determined within a scope of 10<11>-5X10<15> according to a capacity value using implantation region and a resistance value of wiring. Then with the mask of poly Si layer 8, N<+> layer 10 and P<+> layer 11 are formed in sequence so that a structure is obtained in which depression type FET and are connected to FET of each N and P channel respectively. As FET and function as capacitive or crossing wiring, these circuit elements are formed simultaneously in separate structure formed by selective oxidation.
JP9772580A 1980-07-17 1980-07-17 Semiconductor integrated circuit Pending JPS5723243A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9772580A JPS5723243A (en) 1980-07-17 1980-07-17 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9772580A JPS5723243A (en) 1980-07-17 1980-07-17 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5723243A true JPS5723243A (en) 1982-02-06

Family

ID=14199856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9772580A Pending JPS5723243A (en) 1980-07-17 1980-07-17 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5723243A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075240A (en) * 1989-04-19 1991-12-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor device manufactured by using conductive ion implantation mask

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50107871A (en) * 1974-01-30 1975-08-25
JPS5293282A (en) * 1976-01-30 1977-08-05 Matsushita Electronics Corp Manufacture for semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50107871A (en) * 1974-01-30 1975-08-25
JPS5293282A (en) * 1976-01-30 1977-08-05 Matsushita Electronics Corp Manufacture for semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075240A (en) * 1989-04-19 1991-12-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor device manufactured by using conductive ion implantation mask

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