JPS5721192A - Signal separation circuit - Google Patents
Signal separation circuitInfo
- Publication number
- JPS5721192A JPS5721192A JP9565480A JP9565480A JPS5721192A JP S5721192 A JPS5721192 A JP S5721192A JP 9565480 A JP9565480 A JP 9565480A JP 9565480 A JP9565480 A JP 9565480A JP S5721192 A JPS5721192 A JP S5721192A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- given
- outputs
- delay line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/642—Multi-standard receivers
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Processing Of Color Television Signals (AREA)
Abstract
PURPOSE:To enable to receive the signals other than NTSC, by switching the original signal from a delay line and a signal inverted to the original signal from the result of phase comparison between the reference signal and the horizontal detection signal. CONSTITUTION:A video signal 1 is given to a 1H delay line 3 and a 4 fsc clock oscillation circuit 14, which outputs a 2 fsc clock 15. The clock 15 is given to a 1/455 frequency division circuit 16, which outputs the reference signal 21 of 2/455 fsc to a phase comparison circuit 19. On the other hand, a horizontal detection circuit 22 outputs one hoizontal detection signal 21 from a horizontal flyback signal 23 to a circuit 19. The circuit 19 compares both input signals, and if they are coincided, the output signal 4 on a delay line 3 is given to an addition circuit 5 with a Mode discrimination circuit 24, and if not coincided, an inversion signal 11 is given to the circuit 24. Another input to the circuit 1 is the original signal 1 and two times the Y signal 6 is obtained from the circuit 1. The signal 6 is 1/2 times at a division circuit 7 to obtain the Y signal 8. The C signal 10 is obtained from a substraction circuit 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9565480A JPS5721192A (en) | 1980-07-15 | 1980-07-15 | Signal separation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9565480A JPS5721192A (en) | 1980-07-15 | 1980-07-15 | Signal separation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5721192A true JPS5721192A (en) | 1982-02-03 |
Family
ID=14143480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9565480A Pending JPS5721192A (en) | 1980-07-15 | 1980-07-15 | Signal separation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5721192A (en) |
-
1980
- 1980-07-15 JP JP9565480A patent/JPS5721192A/en active Pending
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