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JPS57211659A - Memory access controller - Google Patents

Memory access controller

Info

Publication number
JPS57211659A
JPS57211659A JP56097140A JP9714081A JPS57211659A JP S57211659 A JPS57211659 A JP S57211659A JP 56097140 A JP56097140 A JP 56097140A JP 9714081 A JP9714081 A JP 9714081A JP S57211659 A JPS57211659 A JP S57211659A
Authority
JP
Japan
Prior art keywords
busy
bank
access
port
priority level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56097140A
Other languages
Japanese (ja)
Other versions
JPH0330175B2 (en
Inventor
Mikio Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56097140A priority Critical patent/JPS57211659A/en
Publication of JPS57211659A publication Critical patent/JPS57211659A/en
Publication of JPH0330175B2 publication Critical patent/JPH0330175B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To improve the memory access, by selecting an access request port, where the bank is not busy, having a low priority level when the bank of an access request port having a high priority level is busy. CONSTITUTION:The address of each of ports 10-13 is inputted to a busy check circuit 22 and bus contention check circuit 23, and the bank is checked for the busy state, and the address bus is checked for contention, and results are inputted to a priority and bus selecting circuit 24. The output of the circuit 24 is transmitted to a corresponding one of memory units 5-8 through a corresponding one of registers 18-21. However, if the bank is busy for the access request of a port having a high priority level when plural access sources request the access to the same memory unit simultaneously, the access request of a port, where the bank is not busy, having a low priority level is selected.
JP56097140A 1981-06-23 1981-06-23 Memory access controller Granted JPS57211659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56097140A JPS57211659A (en) 1981-06-23 1981-06-23 Memory access controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56097140A JPS57211659A (en) 1981-06-23 1981-06-23 Memory access controller

Publications (2)

Publication Number Publication Date
JPS57211659A true JPS57211659A (en) 1982-12-25
JPH0330175B2 JPH0330175B2 (en) 1991-04-26

Family

ID=14184258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56097140A Granted JPS57211659A (en) 1981-06-23 1981-06-23 Memory access controller

Country Status (1)

Country Link
JP (1) JPS57211659A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60146344A (en) * 1984-01-10 1985-08-02 Mitsubishi Electric Corp Priority deciding device
FR2641096A1 (en) * 1988-12-27 1990-06-29 Nec Corp Method and device for monitoring access requests to the memory unit in a data processing system
JPH02245858A (en) * 1989-03-20 1990-10-01 Fujitsu Ltd Data transfer controller
JPH03238539A (en) * 1990-02-15 1991-10-24 Nec Corp Memory access controller
JP2006155220A (en) * 2004-11-29 2006-06-15 Canon Inc Semiconductor integrated circuit and access control method therefor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60146344A (en) * 1984-01-10 1985-08-02 Mitsubishi Electric Corp Priority deciding device
FR2641096A1 (en) * 1988-12-27 1990-06-29 Nec Corp Method and device for monitoring access requests to the memory unit in a data processing system
JPH02245858A (en) * 1989-03-20 1990-10-01 Fujitsu Ltd Data transfer controller
JPH03238539A (en) * 1990-02-15 1991-10-24 Nec Corp Memory access controller
JP2006155220A (en) * 2004-11-29 2006-06-15 Canon Inc Semiconductor integrated circuit and access control method therefor
JP4726187B2 (en) * 2004-11-29 2011-07-20 キヤノン株式会社 Semiconductor integrated circuit

Also Published As

Publication number Publication date
JPH0330175B2 (en) 1991-04-26

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