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JPS57201947A - Preventing method for interruption malfunction of computer - Google Patents

Preventing method for interruption malfunction of computer

Info

Publication number
JPS57201947A
JPS57201947A JP56086620A JP8662081A JPS57201947A JP S57201947 A JPS57201947 A JP S57201947A JP 56086620 A JP56086620 A JP 56086620A JP 8662081 A JP8662081 A JP 8662081A JP S57201947 A JPS57201947 A JP S57201947A
Authority
JP
Japan
Prior art keywords
interruption
request signal
malfunction
computer
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56086620A
Other languages
Japanese (ja)
Other versions
JPS6136665B2 (en
Inventor
Naomi Tomizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIHON DENSHI KIKI KK
Hitachi Unisia Automotive Ltd
Original Assignee
NIHON DENSHI KIKI KK
Japan Electronic Control Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIHON DENSHI KIKI KK, Japan Electronic Control Systems Co Ltd filed Critical NIHON DENSHI KIKI KK
Priority to JP56086620A priority Critical patent/JPS57201947A/en
Publication of JPS57201947A publication Critical patent/JPS57201947A/en
Publication of JPS6136665B2 publication Critical patent/JPS6136665B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To evade interruption processing operation due to noise by confirming an interruption request signal and then performing actual interruption program processing during interruption processing. CONSTITUTION:At a microcomputer 2, an interruption request signal from an external input and output equipment is supplied to the interruption terminal INT and input port A. In the microcomputer 2, an interruption confirming block for conforming whether the signal supplied to the interruption terminal INT is the interruption request signal or not is processed firstly and then an actual interruption processing program is executed in accordance with the result of said confirmation.
JP56086620A 1981-06-05 1981-06-05 Preventing method for interruption malfunction of computer Granted JPS57201947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56086620A JPS57201947A (en) 1981-06-05 1981-06-05 Preventing method for interruption malfunction of computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56086620A JPS57201947A (en) 1981-06-05 1981-06-05 Preventing method for interruption malfunction of computer

Publications (2)

Publication Number Publication Date
JPS57201947A true JPS57201947A (en) 1982-12-10
JPS6136665B2 JPS6136665B2 (en) 1986-08-19

Family

ID=13892060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56086620A Granted JPS57201947A (en) 1981-06-05 1981-06-05 Preventing method for interruption malfunction of computer

Country Status (1)

Country Link
JP (1) JPS57201947A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5920029A (en) * 1982-07-27 1984-02-01 Fuji Xerox Co Ltd Taking-in device of sensor signal
JPS60243751A (en) * 1984-05-17 1985-12-03 Meidensha Electric Mfg Co Ltd Supervisory circuit of incorrect interruption in computer
JPS6195454A (en) * 1984-10-17 1986-05-14 Matsushita Electric Ind Co Ltd Microcomputer
JPS61110242A (en) * 1984-11-02 1986-05-28 Sanyo Electric Co Ltd Method for detecting interrupt signal of microcomputer
JPH03156553A (en) * 1989-11-14 1991-07-04 Hitachi Ltd DMA control device and information processing system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5920029A (en) * 1982-07-27 1984-02-01 Fuji Xerox Co Ltd Taking-in device of sensor signal
JPS60243751A (en) * 1984-05-17 1985-12-03 Meidensha Electric Mfg Co Ltd Supervisory circuit of incorrect interruption in computer
JPS6195454A (en) * 1984-10-17 1986-05-14 Matsushita Electric Ind Co Ltd Microcomputer
JPS61110242A (en) * 1984-11-02 1986-05-28 Sanyo Electric Co Ltd Method for detecting interrupt signal of microcomputer
JPH03156553A (en) * 1989-11-14 1991-07-04 Hitachi Ltd DMA control device and information processing system

Also Published As

Publication number Publication date
JPS6136665B2 (en) 1986-08-19

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