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JPS5654508A - Signal processor - Google Patents

Signal processor

Info

Publication number
JPS5654508A
JPS5654508A JP13025179A JP13025179A JPS5654508A JP S5654508 A JPS5654508 A JP S5654508A JP 13025179 A JP13025179 A JP 13025179A JP 13025179 A JP13025179 A JP 13025179A JP S5654508 A JPS5654508 A JP S5654508A
Authority
JP
Japan
Prior art keywords
signal
lag
linear lag
operator
linear
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13025179A
Other languages
Japanese (ja)
Inventor
Sadao Okuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shimadzu Corp
Original Assignee
Shimadzu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shimadzu Corp filed Critical Shimadzu Corp
Priority to JP13025179A priority Critical patent/JPS5654508A/en
Publication of JPS5654508A publication Critical patent/JPS5654508A/en
Pending legal-status Critical Current

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  • Feedback Control In General (AREA)

Abstract

PURPOSE: To reduce a time lag by performing processing by combining a linear lag operator according to fluctuations of an analog signal.
CONSTITUTION: Deviation warning setter B1, when the difference between input signal X0 and output signal X1 of linear lag operator A1 is less than X11, outputs a signal to supply signal X0 to the input of linear lag operator A3. Deviation warning setter B2, when the difference between input signal X0 and output signal X2 of linear lag operator A2 is greater than X21, outputs a signal to supply signal X2 to the input of linear lag operator A3. Time constants L1, L2 and L3 of linear lag operators A1, A2 and A3 are so set that L1<L3<L2. Those linear lag operators can be connected so that attenuation and lag are minimized for effective fluctuations and attenuation is done as usual for ineffective fluctuations.
COPYRIGHT: (C)1981,JPO&Japio
JP13025179A 1979-10-09 1979-10-09 Signal processor Pending JPS5654508A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13025179A JPS5654508A (en) 1979-10-09 1979-10-09 Signal processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13025179A JPS5654508A (en) 1979-10-09 1979-10-09 Signal processor

Publications (1)

Publication Number Publication Date
JPS5654508A true JPS5654508A (en) 1981-05-14

Family

ID=15029765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13025179A Pending JPS5654508A (en) 1979-10-09 1979-10-09 Signal processor

Country Status (1)

Country Link
JP (1) JPS5654508A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154511U (en) * 1986-03-19 1987-10-01
JPH02180395A (en) * 1988-12-29 1990-07-13 Junichi Tsuzuki Method for building pipe

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154511U (en) * 1986-03-19 1987-10-01
JPH02180395A (en) * 1988-12-29 1990-07-13 Junichi Tsuzuki Method for building pipe

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