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JPS57201026A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57201026A
JPS57201026A JP8564281A JP8564281A JPS57201026A JP S57201026 A JPS57201026 A JP S57201026A JP 8564281 A JP8564281 A JP 8564281A JP 8564281 A JP8564281 A JP 8564281A JP S57201026 A JPS57201026 A JP S57201026A
Authority
JP
Japan
Prior art keywords
film
aluminum
thin
etched
low temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8564281A
Other languages
Japanese (ja)
Inventor
Hiroshi Norimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP8564281A priority Critical patent/JPS57201026A/en
Publication of JPS57201026A publication Critical patent/JPS57201026A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To accurately obtain an aluminum electrode wiring pattern by providing a conductive layer between insulating layers under aluminum. CONSTITUTION:A thin conductive film 13 (e.g., thin titanium film) having slow etching speed to aluminum is formed on an insulating film 12 on the surface of a semiconductor substrate 11. An aluminum film 14 is formed on the film, the unnecessary part of the film 14 is etched by a resist pattern 15 with low temperature plasma using gas containing chlorine gas, and the thin film 15 except under the remaining aluminum film is etched by the low temperature plasma with gas containing no chlorine.
JP8564281A 1981-06-05 1981-06-05 Manufacture of semiconductor device Pending JPS57201026A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8564281A JPS57201026A (en) 1981-06-05 1981-06-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8564281A JPS57201026A (en) 1981-06-05 1981-06-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57201026A true JPS57201026A (en) 1982-12-09

Family

ID=13864474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8564281A Pending JPS57201026A (en) 1981-06-05 1981-06-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57201026A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61258454A (en) * 1985-03-19 1986-11-15 フエアチヤイルド　セミコンダクタ　コ−ポレ−シヨン Thick bus metalization mutual connection structural body with reduced bus zone
JPS62154628A (en) * 1985-12-26 1987-07-09 Matsushita Electric Ind Co Ltd Dry etching method
EP1077481A2 (en) * 1999-08-16 2001-02-21 Applied Komatsu Technology, Inc. Etching aluminium over refractory metal with successive plasmas

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61258454A (en) * 1985-03-19 1986-11-15 フエアチヤイルド　セミコンダクタ　コ−ポレ−シヨン Thick bus metalization mutual connection structural body with reduced bus zone
JPS62154628A (en) * 1985-12-26 1987-07-09 Matsushita Electric Ind Co Ltd Dry etching method
EP1077481A2 (en) * 1999-08-16 2001-02-21 Applied Komatsu Technology, Inc. Etching aluminium over refractory metal with successive plasmas
EP1077481A3 (en) * 1999-08-16 2002-01-09 AKT, Inc. Etching aluminium over refractory metal with successive plasmas
US6472329B1 (en) 1999-08-16 2002-10-29 Applied Komatsu Technology, Inc. Etching aluminum over refractory metal with successive plasmas

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