JPS5720009A - Preliminary agc circuit - Google Patents
Preliminary agc circuitInfo
- Publication number
- JPS5720009A JPS5720009A JP9380880A JP9380880A JPS5720009A JP S5720009 A JPS5720009 A JP S5720009A JP 9380880 A JP9380880 A JP 9380880A JP 9380880 A JP9380880 A JP 9380880A JP S5720009 A JPS5720009 A JP S5720009A
- Authority
- JP
- Japan
- Prior art keywords
- level
- gain
- counter
- signal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003247 decreasing effect Effects 0.000 abstract 3
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
PURPOSE:To compress level variations of an input signal momentarily by decreasing the gain width of an amplifier by a constant width for each time when the amplitude of an output signal is found greater than a criterion level, by making a counter goes up. CONSTITUTION:When the peak level of an output signal S2 appearing at an output terminal 2 becomes greater than a criterion level applied to an input terminal 3, an enabling signal input to a counter 10 goes to a 0 and outputs Q0-Q3 of the counter 10 increase. Consequently, the gain of a variable amplifier composed of operation amplifiers 17 and 25, analog switches 18 and 26, etc., is decreased by a constant width for each time. The gain of this variable amplifier is decreased until the peak level of the signal S2 falls below the criterion level. This operation is speeded by setting the frequency of clock pulses C applied to a terminal 6 high enough. If an input signal S1 applied to the input terminal 1 is intercepted during said opration, a level comparing circuit 7 detects that and resets outputs Q0-Q3 of the counter 10 to 0s, maximizing the gain of the variable amplifier again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9380880A JPS5720009A (en) | 1980-07-11 | 1980-07-11 | Preliminary agc circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9380880A JPS5720009A (en) | 1980-07-11 | 1980-07-11 | Preliminary agc circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5720009A true JPS5720009A (en) | 1982-02-02 |
Family
ID=14092698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9380880A Pending JPS5720009A (en) | 1980-07-11 | 1980-07-11 | Preliminary agc circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5720009A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62141226U (en) * | 1986-02-26 | 1987-09-05 | ||
| JPH01169370A (en) * | 1987-12-25 | 1989-07-04 | Hioki Ee Corp | Measuring range setter |
-
1980
- 1980-07-11 JP JP9380880A patent/JPS5720009A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62141226U (en) * | 1986-02-26 | 1987-09-05 | ||
| JPH01169370A (en) * | 1987-12-25 | 1989-07-04 | Hioki Ee Corp | Measuring range setter |
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