JPS57193065A - Insulated gate field effect transistor - Google Patents
Insulated gate field effect transistorInfo
- Publication number
- JPS57193065A JPS57193065A JP56078511A JP7851181A JPS57193065A JP S57193065 A JPS57193065 A JP S57193065A JP 56078511 A JP56078511 A JP 56078511A JP 7851181 A JP7851181 A JP 7851181A JP S57193065 A JPS57193065 A JP S57193065A
- Authority
- JP
- Japan
- Prior art keywords
- field effect
- effect transistor
- layer
- insulated gate
- gate field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
Abstract
PURPOSE:To decrease a threshold voltage of an enhancement type IGFET without applying any operation to the parameter except the length of an inverted layer by forming a depletion layer between a drain part and a source part in a range that is not coupled directly between the drain part and the source part. CONSTITUTION:A drain part 2 and a source part 3 are diffused at the prescribed interval on the surface side of an Si substrate 1, a gate 4 formed of a gate oxidized film 6 and a gate electrode 7 disposed on the film 6 is formed on the surface of a substrate 1 between the part 2 and the part 3, thereby forming an enhancement type IGFET. In this structure, a depletion layer 5 is formed shallower than he parts 2, 3 in a range that is not coupled directly from the end of the part 2 to the end of the part 3. At this time, the layer 5 may be extended from either end toward the center, or may be provided at the intermediate between the ends. In this manner, a threshold voltage is lowered, thereby decreasing the power consumption.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56078511A JPS57193065A (en) | 1981-05-22 | 1981-05-22 | Insulated gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56078511A JPS57193065A (en) | 1981-05-22 | 1981-05-22 | Insulated gate field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57193065A true JPS57193065A (en) | 1982-11-27 |
Family
ID=13663957
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56078511A Pending JPS57193065A (en) | 1981-05-22 | 1981-05-22 | Insulated gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57193065A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1989012910A1 (en) * | 1988-06-23 | 1989-12-28 | Dallas Semiconductor Corporation | Enclosed buried channel transistor |
| US4943537A (en) * | 1988-06-23 | 1990-07-24 | Dallas Semiconductor Corporation | CMOS integrated circuit with reduced susceptibility to PMOS punchthrough |
| US5122474A (en) * | 1988-06-23 | 1992-06-16 | Dallas Semiconductor Corporation | Method of fabricating a CMOS IC with reduced susceptibility to PMOS punchthrough |
-
1981
- 1981-05-22 JP JP56078511A patent/JPS57193065A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1989012910A1 (en) * | 1988-06-23 | 1989-12-28 | Dallas Semiconductor Corporation | Enclosed buried channel transistor |
| US4906588A (en) * | 1988-06-23 | 1990-03-06 | Dallas Semiconductor Corporation | Enclosed buried channel transistor |
| US4943537A (en) * | 1988-06-23 | 1990-07-24 | Dallas Semiconductor Corporation | CMOS integrated circuit with reduced susceptibility to PMOS punchthrough |
| US5122474A (en) * | 1988-06-23 | 1992-06-16 | Dallas Semiconductor Corporation | Method of fabricating a CMOS IC with reduced susceptibility to PMOS punchthrough |
| US5688722A (en) * | 1988-06-23 | 1997-11-18 | Dallas Semiconductor Corporation | CMOS integrated circuit with reduced susceptibility to PMOS punchthrough |
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