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JPS57190415A - Timing extracting circuit - Google Patents

Timing extracting circuit

Info

Publication number
JPS57190415A
JPS57190415A JP56074301A JP7430181A JPS57190415A JP S57190415 A JPS57190415 A JP S57190415A JP 56074301 A JP56074301 A JP 56074301A JP 7430181 A JP7430181 A JP 7430181A JP S57190415 A JPS57190415 A JP S57190415A
Authority
JP
Japan
Prior art keywords
circuit
signal
polarity
differential
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56074301A
Other languages
Japanese (ja)
Other versions
JPS643372B2 (en
Inventor
Botaro Hirosaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56074301A priority Critical patent/JPS57190415A/en
Priority to CA000402991A priority patent/CA1180416A/en
Priority to US06/379,408 priority patent/US4423518A/en
Publication of JPS57190415A publication Critical patent/JPS57190415A/en
Publication of JPS643372B2 publication Critical patent/JPS643372B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0054Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0062Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K9/00Demodulating pulses which have been modulated with a continuously-variable signal
    • H03K9/02Demodulating pulses which have been modulated with a continuously-variable signal of amplitude-modulated pulses

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To simplify circuit configuration and to stabilize the operation of the titled circuit even if a received waveform is deteriorated. CONSTITUTION:A PAM signal y(t) received from an input terminal 1 is inputted to a delay differential circuit 2 and a polarity deciding circuit 3. The delay differential signal y(t) and an input signal y(t-T) received just 1 clock T before the input signal y(t) and outputs the differential circuit 2 finds the difference between the input signal and the polarity deciding ciruit 3 decides the polarity of the difference between the input signal y(t) and a prescribed threshold level by a timing signal outputted from a voltage controlling oscillator 6. A gate circuit 4 sends the differential signal outputted from the delay differential circuit 2 to a loop filter 5 as it is when the output of the polarity deciding circuit 3 is positive, and sends the differential signal to the loop filter 5 after inverting the polarity of the differential signal in case of the negative output. The voltage controlling oscillator 6 generates a timing signal whose oscillation frequency is controlled by the control voltage smoothed by the loop filter 5 to give the polarity deciding timing to the polarity deciding circuit 3.
JP56074301A 1981-05-19 1981-05-19 Timing extracting circuit Granted JPS57190415A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP56074301A JPS57190415A (en) 1981-05-19 1981-05-19 Timing extracting circuit
CA000402991A CA1180416A (en) 1981-05-19 1982-05-14 Timing recovery circuit
US06/379,408 US4423518A (en) 1981-05-19 1982-05-18 Timing recovery circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56074301A JPS57190415A (en) 1981-05-19 1981-05-19 Timing extracting circuit

Publications (2)

Publication Number Publication Date
JPS57190415A true JPS57190415A (en) 1982-11-24
JPS643372B2 JPS643372B2 (en) 1989-01-20

Family

ID=13543165

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56074301A Granted JPS57190415A (en) 1981-05-19 1981-05-19 Timing extracting circuit

Country Status (1)

Country Link
JP (1) JPS57190415A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6693180B2 (en) 2016-03-09 2020-05-13 ヤマハ株式会社 Recording data analysis method and recording data analysis device

Also Published As

Publication number Publication date
JPS643372B2 (en) 1989-01-20

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