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JPS5549056A - Clock regenerating circuit - Google Patents

Clock regenerating circuit

Info

Publication number
JPS5549056A
JPS5549056A JP12223778A JP12223778A JPS5549056A JP S5549056 A JPS5549056 A JP S5549056A JP 12223778 A JP12223778 A JP 12223778A JP 12223778 A JP12223778 A JP 12223778A JP S5549056 A JPS5549056 A JP S5549056A
Authority
JP
Japan
Prior art keywords
circuit
output
burst
beginning
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12223778A
Other languages
Japanese (ja)
Inventor
Iwao Eguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12223778A priority Critical patent/JPS5549056A/en
Publication of JPS5549056A publication Critical patent/JPS5549056A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To make it possible to regenerate a clock signal with a few noises after a period of transient response by quickening the transient response in the beginning of a burst, by alternating PLL with excellent noise-proof characteristics and a broad-bank resonance circuit. CONSTITUTION:An input signal to terminal 101 is supplied to clock extraction circuit 1, where its clock component is extracted. Its output has its nose component removed by resonance circuit 4 and is made into a clock signal of constant amplitude by amplitude limiting circuit 3. To quicken a rise in phase in the beginning of a burst, the band width of circuit 4 is widened and when an output signal from circuit 3 is inputted to PLL10, the output phase of voltage control oscillation circuit 6 changes in the beginning of the burst. This change is expressed as a voltage in the output of phase comparator circuit 5. Then, detection circuit 8, when detecting this voltage exceeding a certain range, operates switching circuit 9, so that a signal obtained switching the output of circuit 6 to that of circuit 3 will appear at terminal 102.
JP12223778A 1978-10-03 1978-10-03 Clock regenerating circuit Pending JPS5549056A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12223778A JPS5549056A (en) 1978-10-03 1978-10-03 Clock regenerating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12223778A JPS5549056A (en) 1978-10-03 1978-10-03 Clock regenerating circuit

Publications (1)

Publication Number Publication Date
JPS5549056A true JPS5549056A (en) 1980-04-08

Family

ID=14830967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12223778A Pending JPS5549056A (en) 1978-10-03 1978-10-03 Clock regenerating circuit

Country Status (1)

Country Link
JP (1) JPS5549056A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05175948A (en) * 1991-12-24 1993-07-13 Nec Corp Timing circuit for digital transmission system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05175948A (en) * 1991-12-24 1993-07-13 Nec Corp Timing circuit for digital transmission system

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