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JPS57187728A - Data transfer control method - Google Patents

Data transfer control method

Info

Publication number
JPS57187728A
JPS57187728A JP56072807A JP7280781A JPS57187728A JP S57187728 A JPS57187728 A JP S57187728A JP 56072807 A JP56072807 A JP 56072807A JP 7280781 A JP7280781 A JP 7280781A JP S57187728 A JPS57187728 A JP S57187728A
Authority
JP
Japan
Prior art keywords
data
order
request
storage device
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56072807A
Other languages
Japanese (ja)
Inventor
Mitsuaki Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56072807A priority Critical patent/JPS57187728A/en
Publication of JPS57187728A publication Critical patent/JPS57187728A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To arrange and store data in a buffer storage device of the data request source in the order of data request even if data is transferred in the order different from the order of data request, by providing a means for transmission of signals which indicate storage addresses in the data request source. CONSTITUTION:When a request start signal 21 is outputted from an operation controlling circuit 2, a request controlling circuit 3 is started, and contents of a buffer address counter 13 are updated. A data request signal 8 is sent from the request controlling circuit 3 to storage devices 5-7 in the order of RQ1-RQ3, and an address signal is sent from an address register 4 in the order of AD1- AD3 to indicate addresses in storage devices where requested information should be stored. After the storage device 5 finds that the address AD1 for RQ1 is in the storage device 5 itself, the storage device 5 starts the access operation to AD1 and stores contents N of an output signal 22 of the buffer address counter 13 in a data storage address register 51 and transmits contents N when information DT1 is outputted.
JP56072807A 1981-05-14 1981-05-14 Data transfer control method Pending JPS57187728A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56072807A JPS57187728A (en) 1981-05-14 1981-05-14 Data transfer control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56072807A JPS57187728A (en) 1981-05-14 1981-05-14 Data transfer control method

Publications (1)

Publication Number Publication Date
JPS57187728A true JPS57187728A (en) 1982-11-18

Family

ID=13500032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56072807A Pending JPS57187728A (en) 1981-05-14 1981-05-14 Data transfer control method

Country Status (1)

Country Link
JP (1) JPS57187728A (en)

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