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JPS5718348A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS5718348A
JPS5718348A JP9343580A JP9343580A JPS5718348A JP S5718348 A JPS5718348 A JP S5718348A JP 9343580 A JP9343580 A JP 9343580A JP 9343580 A JP9343580 A JP 9343580A JP S5718348 A JPS5718348 A JP S5718348A
Authority
JP
Japan
Prior art keywords
lead frame
integrated circuit
chip
circuit device
circumference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9343580A
Other languages
Japanese (ja)
Inventor
Mitsuru Nitta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9343580A priority Critical patent/JPS5718348A/en
Publication of JPS5718348A publication Critical patent/JPS5718348A/en
Pending legal-status Critical Current

Links

Classifications

    • H10W70/453—
    • H10W72/701—

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To manufacture a film carrier type IC at low cost by a method wherein an integrated circuit chip is connected to a lead frame adhered to a film type insulating tape, input and output pins are connected directly to the lead frame and the circumference of the chip is molded with a resin. CONSTITUTION:The integrated circuit chip 3 is connected to the lead frame 2 adhered to the film type insulating tape 1. The connecting pins 5 are connected at pin connecting parts 7 to test pads 4 connected to the other end of the lead frame by direct soldering or by calking. Moreover the circumference of the chip 3 is covered with the hardening resin 6 to mold and to form the film carrier type insulated circuit device. Accordingly no substrate is necessitated, number of process is reduced and cost is lowered.
JP9343580A 1980-07-09 1980-07-09 Integrated circuit device Pending JPS5718348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9343580A JPS5718348A (en) 1980-07-09 1980-07-09 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9343580A JPS5718348A (en) 1980-07-09 1980-07-09 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5718348A true JPS5718348A (en) 1982-01-30

Family

ID=14082225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9343580A Pending JPS5718348A (en) 1980-07-09 1980-07-09 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5718348A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63307762A (en) * 1987-06-09 1988-12-15 Mitsubishi Electric Corp Semiconductor device
JPH03293739A (en) * 1990-04-12 1991-12-25 Toshiba Corp Semiconductor device
US7038315B2 (en) * 1995-05-08 2006-05-02 Micron Technology, Inc. Semiconductor chip package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63307762A (en) * 1987-06-09 1988-12-15 Mitsubishi Electric Corp Semiconductor device
JPH03293739A (en) * 1990-04-12 1991-12-25 Toshiba Corp Semiconductor device
US7038315B2 (en) * 1995-05-08 2006-05-02 Micron Technology, Inc. Semiconductor chip package

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