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JPS57183037A - Formation of pattern - Google Patents

Formation of pattern

Info

Publication number
JPS57183037A
JPS57183037A JP6797281A JP6797281A JPS57183037A JP S57183037 A JPS57183037 A JP S57183037A JP 6797281 A JP6797281 A JP 6797281A JP 6797281 A JP6797281 A JP 6797281A JP S57183037 A JPS57183037 A JP S57183037A
Authority
JP
Japan
Prior art keywords
layer
metal
pattern
coated
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6797281A
Other languages
Japanese (ja)
Inventor
Hiroshi Gokan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6797281A priority Critical patent/JPS57183037A/en
Publication of JPS57183037A publication Critical patent/JPS57183037A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To enable to form a T-shaped pattern with an excellent controllability by a method wherein two layers of metal or oxide are formed on elements pinching an auxiliary layer, an aperture is provided on these layers, and a T- shaped pattern of evaporated metal is formed. CONSTITUTION:A metal or oxide layer 11 of d0 in thickness is coated on the active layer 2 that was formed on a substrate, and an auxiliary layer 12 of d1 in thickness is coated on the layer 11 as a control layer of pattern intervals. Besides, a metal or oxide layer 13 is coated on the above, a photoresist material 14 is applied on the layer 13, and a hole of WH in width is provided. Then, using this mask pattern, an aperture is provided on the layer 13, an ion beam is irradiated in shower form, and an aperture is provided on the layer 12. The sputtered layer 12 is coated on the aperture wall surface located between the layer 13 and the resist 14, and a wall 12' is formed. Accordingly, the width WL is reduced in proportion to the film thickness d1. Then, an etching process is performed on the layers 12 and 12', a metal 15 is deposited on the whole surface while the layers 11-13 are successively removed, and then a T-shaped gate pattern can be obtained.
JP6797281A 1981-05-06 1981-05-06 Formation of pattern Pending JPS57183037A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6797281A JPS57183037A (en) 1981-05-06 1981-05-06 Formation of pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6797281A JPS57183037A (en) 1981-05-06 1981-05-06 Formation of pattern

Publications (1)

Publication Number Publication Date
JPS57183037A true JPS57183037A (en) 1982-11-11

Family

ID=13360406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6797281A Pending JPS57183037A (en) 1981-05-06 1981-05-06 Formation of pattern

Country Status (1)

Country Link
JP (1) JPS57183037A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59136933A (en) * 1983-01-13 1984-08-06 コミツサリア・タ・レネルギ−・アトミ−ク Method of producing integrated circuit conductor using planar technique
JPS60202924A (en) * 1984-03-28 1985-10-14 Hitachi Ltd Fine film formation method and device
JPS6177370A (en) * 1984-09-21 1986-04-19 Fujitsu Ltd Pattern formation method
US5288654A (en) * 1990-12-26 1994-02-22 Mitsubishi Denki Kabushiki Kaisha Method of making a mushroom-shaped gate electrode of semiconductor device
JPH0689907A (en) * 1991-05-28 1994-03-29 Hughes Aircraft Co Method for formation of t-shaped gate structure on microelectronic-device substrate
US5563079A (en) * 1992-06-09 1996-10-08 Goldstar Co., Ltd. Method of making a field effect transistor
US6051485A (en) * 1997-04-24 2000-04-18 Siemens Aktiengesellschaft Method of producing a platinum-metal pattern or structure by a lift-off process

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59136933A (en) * 1983-01-13 1984-08-06 コミツサリア・タ・レネルギ−・アトミ−ク Method of producing integrated circuit conductor using planar technique
JPS60202924A (en) * 1984-03-28 1985-10-14 Hitachi Ltd Fine film formation method and device
JPS6177370A (en) * 1984-09-21 1986-04-19 Fujitsu Ltd Pattern formation method
US5288654A (en) * 1990-12-26 1994-02-22 Mitsubishi Denki Kabushiki Kaisha Method of making a mushroom-shaped gate electrode of semiconductor device
JPH0689907A (en) * 1991-05-28 1994-03-29 Hughes Aircraft Co Method for formation of t-shaped gate structure on microelectronic-device substrate
US5563079A (en) * 1992-06-09 1996-10-08 Goldstar Co., Ltd. Method of making a field effect transistor
US6051485A (en) * 1997-04-24 2000-04-18 Siemens Aktiengesellschaft Method of producing a platinum-metal pattern or structure by a lift-off process

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