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JPS57180173A - Mis transistor and manufacture thereof - Google Patents

Mis transistor and manufacture thereof

Info

Publication number
JPS57180173A
JPS57180173A JP56065539A JP6553981A JPS57180173A JP S57180173 A JPS57180173 A JP S57180173A JP 56065539 A JP56065539 A JP 56065539A JP 6553981 A JP6553981 A JP 6553981A JP S57180173 A JPS57180173 A JP S57180173A
Authority
JP
Japan
Prior art keywords
poly
ion
laser
gate
implanted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56065539A
Other languages
Japanese (ja)
Inventor
Junji Sakurai
Seiichiro Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56065539A priority Critical patent/JPS57180173A/en
Publication of JPS57180173A publication Critical patent/JPS57180173A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]

Abstract

PURPOSE:To improve the performance of MOSFET by a method wherein the poly Si gate, the source and the drain are separately annealed using laser under the respective optimum conditions. CONSTITUTION:The field oxide film 2', the gate oxide film 2'' and the P<+> channel cut P'' are provided on the P type Si substrate and the surface is covered with the poly Si 3' and implanted with the B<+> ion to control the threshold level. Next after annealing the surface with the rectangular laser beam L, the poly Si gate electrode 3 is formed by means of patterning while the exposed substrate is covered with the SiO2 2. Then the surface is implanted with the P<+> ion and further radiated by the laser pulse to activate the P<+> ion in the n<+> source, the drain and the poly Si gate. The characteristics of the gate electrode 3 are subject to no change after the two times radiation, because each laser annealing is selectively performed meeting the optimum requirements in terms of respective wavelength, output, waveform and the like. The beams of ion, electron or the like in addn. to laser may be effective.
JP56065539A 1981-04-30 1981-04-30 Mis transistor and manufacture thereof Pending JPS57180173A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56065539A JPS57180173A (en) 1981-04-30 1981-04-30 Mis transistor and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56065539A JPS57180173A (en) 1981-04-30 1981-04-30 Mis transistor and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS57180173A true JPS57180173A (en) 1982-11-06

Family

ID=13289915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56065539A Pending JPS57180173A (en) 1981-04-30 1981-04-30 Mis transistor and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS57180173A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274885B1 (en) 1994-12-16 2001-08-14 Semiconductor Energy Laboratory Co., Ltd. Active matrix display device with TFTs of different refractive index
US6808974B2 (en) 2001-05-15 2004-10-26 International Business Machines Corporation CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regions

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274885B1 (en) 1994-12-16 2001-08-14 Semiconductor Energy Laboratory Co., Ltd. Active matrix display device with TFTs of different refractive index
KR100393949B1 (en) * 1994-12-16 2003-08-09 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and active matrix display device
US6808974B2 (en) 2001-05-15 2004-10-26 International Business Machines Corporation CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regions

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