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JPS5715286A - Memory device - Google Patents

Memory device

Info

Publication number
JPS5715286A
JPS5715286A JP8775080A JP8775080A JPS5715286A JP S5715286 A JPS5715286 A JP S5715286A JP 8775080 A JP8775080 A JP 8775080A JP 8775080 A JP8775080 A JP 8775080A JP S5715286 A JPS5715286 A JP S5715286A
Authority
JP
Japan
Prior art keywords
refreshing
data
same
cycle
rams
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8775080A
Other languages
Japanese (ja)
Inventor
Noriyuki Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8775080A priority Critical patent/JPS5715286A/en
Publication of JPS5715286A publication Critical patent/JPS5715286A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To eliminate operation delay due to confliction with refreshing operation while using a dynamic RAM as a storing element, by reading out data from either one of a couple of dynamic RAMs stored with the same data which is not in a refreshing cycle. CONSTITUTION:A couple of dynamic RAMs 1 and 2 whose storage contents are the same and a refreshment control circuit 3 which refreshes them through multiplexers 7 and 8 with a refreshing-cycle difference are provided. Then, the same data is written in the same addresses of the RAMs 1 and 2 and from one RAM which is not in a refreshing cycle, the data is read out through a multiplexer 11.
JP8775080A 1980-06-30 1980-06-30 Memory device Pending JPS5715286A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8775080A JPS5715286A (en) 1980-06-30 1980-06-30 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8775080A JPS5715286A (en) 1980-06-30 1980-06-30 Memory device

Publications (1)

Publication Number Publication Date
JPS5715286A true JPS5715286A (en) 1982-01-26

Family

ID=13923605

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8775080A Pending JPS5715286A (en) 1980-06-30 1980-06-30 Memory device

Country Status (1)

Country Link
JP (1) JPS5715286A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4716459A (en) * 1985-01-25 1987-12-29 Nippon Kokan Kabushiki Kaisha Fatigue crack position detection apparatus
US6324113B1 (en) 1999-09-22 2001-11-27 Fujitsu Limited Semiconductor integrated circuit and method of controlling same
JP2004507856A (en) * 2000-08-17 2004-03-11 マイクロン・テクノロジー・インコーポレーテッド Method and system for hiding refresh of dynamic random access memory
JP2012512496A (en) * 2009-05-25 2012-05-31 ソンゼ イ， Apparatus and method for implementing SRAM output characteristics in DRAM

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4716459A (en) * 1985-01-25 1987-12-29 Nippon Kokan Kabushiki Kaisha Fatigue crack position detection apparatus
US6324113B1 (en) 1999-09-22 2001-11-27 Fujitsu Limited Semiconductor integrated circuit and method of controlling same
JP2004507856A (en) * 2000-08-17 2004-03-11 マイクロン・テクノロジー・インコーポレーテッド Method and system for hiding refresh of dynamic random access memory
JP2012512496A (en) * 2009-05-25 2012-05-31 ソンゼ イ， Apparatus and method for implementing SRAM output characteristics in DRAM
EP2437267A4 (en) * 2009-05-25 2013-01-23 Seong Jae Lee Device and method for achieving sram output characteristics from drams

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