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JPS57152064A - Decentralized computer system - Google Patents

Decentralized computer system

Info

Publication number
JPS57152064A
JPS57152064A JP3538581A JP3538581A JPS57152064A JP S57152064 A JPS57152064 A JP S57152064A JP 3538581 A JP3538581 A JP 3538581A JP 3538581 A JP3538581 A JP 3538581A JP S57152064 A JPS57152064 A JP S57152064A
Authority
JP
Japan
Prior art keywords
terminal
processing system
order
multiplexers
transmitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3538581A
Other languages
Japanese (ja)
Other versions
JPS644217B2 (en
Inventor
Yuji Kikuchi
Takakazu Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3538581A priority Critical patent/JPS57152064A/en
Publication of JPS57152064A publication Critical patent/JPS57152064A/en
Publication of JPS644217B2 publication Critical patent/JPS644217B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To minimize a dead time of a processing system, by providing a transmitter between an upper-order processor and a terminal processing system. CONSTITUTION:A transmitter is connected to an upper-order processor consisting of a global memory, an upper-order computer and an upper-order coupling device and also to a plurality of terminal input and output devices. Register groups 35 and 37 are provided at each terminal device so that the information of the terminal device can be written in and read out arbitrarily. Multiplexers 31 and 32 sequentially select the content of the register groups 35 and 37 and output it to a plant controller 33. On the other hand, a logic controller 34 outputs an instruction signal to the multiplexers 31 and 32. Thus, the terminal processing system makes the decentralized processing, collects the information and the upper-order processor can make the operation processing in high speed and accuracy.
JP3538581A 1981-03-13 1981-03-13 Decentralized computer system Granted JPS57152064A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3538581A JPS57152064A (en) 1981-03-13 1981-03-13 Decentralized computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3538581A JPS57152064A (en) 1981-03-13 1981-03-13 Decentralized computer system

Publications (2)

Publication Number Publication Date
JPS57152064A true JPS57152064A (en) 1982-09-20
JPS644217B2 JPS644217B2 (en) 1989-01-25

Family

ID=12440432

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3538581A Granted JPS57152064A (en) 1981-03-13 1981-03-13 Decentralized computer system

Country Status (1)

Country Link
JP (1) JPS57152064A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53132912A (en) * 1977-04-25 1978-11-20 Thomson Csf Exchange controller
JPS57111764A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Count-up device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53132912A (en) * 1977-04-25 1978-11-20 Thomson Csf Exchange controller
JPS57111764A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Count-up device

Also Published As

Publication number Publication date
JPS644217B2 (en) 1989-01-25

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