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JPS5617422A - Interruption control system of information processor - Google Patents

Interruption control system of information processor

Info

Publication number
JPS5617422A
JPS5617422A JP9256379A JP9256379A JPS5617422A JP S5617422 A JPS5617422 A JP S5617422A JP 9256379 A JP9256379 A JP 9256379A JP 9256379 A JP9256379 A JP 9256379A JP S5617422 A JPS5617422 A JP S5617422A
Authority
JP
Japan
Prior art keywords
state
signal
output
circuit
change
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9256379A
Other languages
Japanese (ja)
Inventor
Masao Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9256379A priority Critical patent/JPS5617422A/en
Publication of JPS5617422A publication Critical patent/JPS5617422A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To make it possible to increase greatly an interruption processing speed with simple steps of a program by composing the system of a state change holding register that holds state changes corresponding to respective state signals and a signal line that connects the output of a corresponding circuit to a signal bus.
CONSTITUTION: Initial state signal (a) of input-output unit 4 is set by read-out signal (b) in state holding register 32, whose contents are read by central processor 1 via signal bus 101. Next, a change in (a) is detected by state detecting circuit 31 and its output and the output of interruption mask registe circuit 33 are AND-ed to set state-change holding register circuit 35. This output serves as interruption request signal (d), which allows central processor 1 to perform interruption processing. As a result, the contents of circuit 35 are led to the other output as state-change register signal (f). Signal (f) is read by unit 1, where a bit check is made by an interruption processing program.
COPYRIGHT: (C)1981,JPO&Japio
JP9256379A 1979-07-23 1979-07-23 Interruption control system of information processor Pending JPS5617422A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9256379A JPS5617422A (en) 1979-07-23 1979-07-23 Interruption control system of information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9256379A JPS5617422A (en) 1979-07-23 1979-07-23 Interruption control system of information processor

Publications (1)

Publication Number Publication Date
JPS5617422A true JPS5617422A (en) 1981-02-19

Family

ID=14057886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9256379A Pending JPS5617422A (en) 1979-07-23 1979-07-23 Interruption control system of information processor

Country Status (1)

Country Link
JP (1) JPS5617422A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6131653A (en) * 1984-07-23 1986-02-14 Honda Motor Co Ltd Flow control valve
JPS61166658A (en) * 1985-01-19 1986-07-28 Panafacom Ltd Asynchronous signal processing system for input and output controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6131653A (en) * 1984-07-23 1986-02-14 Honda Motor Co Ltd Flow control valve
JPS61166658A (en) * 1985-01-19 1986-07-28 Panafacom Ltd Asynchronous signal processing system for input and output controller

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