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JPS5714929A - Interface controlling circuit - Google Patents

Interface controlling circuit

Info

Publication number
JPS5714929A
JPS5714929A JP8877780A JP8877780A JPS5714929A JP S5714929 A JPS5714929 A JP S5714929A JP 8877780 A JP8877780 A JP 8877780A JP 8877780 A JP8877780 A JP 8877780A JP S5714929 A JPS5714929 A JP S5714929A
Authority
JP
Japan
Prior art keywords
signal
request
read
write
reception
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8877780A
Other languages
Japanese (ja)
Inventor
Yoshihiro Nitta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8877780A priority Critical patent/JPS5714929A/en
Publication of JPS5714929A publication Critical patent/JPS5714929A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To reduce the queuing time for the subsequent operation, by deciding previously the state of the preceding operation and giving a request to the subsequent operation without waiting the end of the preceding operation in case the subsequent operation receives a limitation by the preceding operation in terms of a transfer of data. CONSTITUTION:A read stack F/F101 is set by the read request signal RRQ and reset with reception of the read action end signal RE. A write F/F102 is set by the write request signal WRQ during a set mode of the F/F101 and reset with reception of the reception permission signal PQ. With these two F/Fs, the fact that the write request is ready to be given before the end of the read action is detected to inform the occurrence of request to a device B. Then the F/F102 delivers a set state (write request) while a timer 105 that monitors the time of read action is delivering the timer signal. Thus the write action is made to wait and then permitted when the set state signal is delivered after the end of the timer signal T.
JP8877780A 1980-06-30 1980-06-30 Interface controlling circuit Pending JPS5714929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8877780A JPS5714929A (en) 1980-06-30 1980-06-30 Interface controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8877780A JPS5714929A (en) 1980-06-30 1980-06-30 Interface controlling circuit

Publications (1)

Publication Number Publication Date
JPS5714929A true JPS5714929A (en) 1982-01-26

Family

ID=13952275

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8877780A Pending JPS5714929A (en) 1980-06-30 1980-06-30 Interface controlling circuit

Country Status (1)

Country Link
JP (1) JPS5714929A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62251865A (en) * 1986-04-23 1987-11-02 Nec Corp Information processor
JPS6347854A (en) * 1986-08-15 1988-02-29 Nec Corp Access control circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62251865A (en) * 1986-04-23 1987-11-02 Nec Corp Information processor
JPS6347854A (en) * 1986-08-15 1988-02-29 Nec Corp Access control circuit
JPH0552977B2 (en) * 1986-08-15 1993-08-06 Nippon Electric Co

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