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JPS567130A - Control system for input/output device - Google Patents

Control system for input/output device

Info

Publication number
JPS567130A
JPS567130A JP8142679A JP8142679A JPS567130A JP S567130 A JPS567130 A JP S567130A JP 8142679 A JP8142679 A JP 8142679A JP 8142679 A JP8142679 A JP 8142679A JP S567130 A JPS567130 A JP S567130A
Authority
JP
Japan
Prior art keywords
drd
input
output device
rank
control device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8142679A
Other languages
Japanese (ja)
Inventor
Kiyoo Moroto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8142679A priority Critical patent/JPS567130A/en
Publication of JPS567130A publication Critical patent/JPS567130A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To avoid resetting of the input/output device by other higher-rank device before sending up the interruption request, by not transmitting the start order to the designated input/output device in case the start order given from the different higher-rank device is detected.
CONSTITUTION: In data record control device DRC, each decode information to indicate the decoded 22 DRD (input/output device) to be selected is applied to one input terminal of AND gate group 26 respectively; and the output of assignment latch circuit 20 for SCD11 (staging disk control device functioning as higher-rank control device) is applied to the other input terminal of group 26. Thus in case the selection order is given from SDC10 to the DRD to which the assignment latch circuit is set by the order given from SDC11, the DRC does not give the selection order to the DRD but performs the internal process and reports to SCD10 that the DRD is now in use. Accordingly when an SDC monitors the interruption request due to the process end for a certain DRD, the DRD is never reset by other SDC.
COPYRIGHT: (C)1981,JPO&Japio
JP8142679A 1979-06-29 1979-06-29 Control system for input/output device Pending JPS567130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8142679A JPS567130A (en) 1979-06-29 1979-06-29 Control system for input/output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8142679A JPS567130A (en) 1979-06-29 1979-06-29 Control system for input/output device

Publications (1)

Publication Number Publication Date
JPS567130A true JPS567130A (en) 1981-01-24

Family

ID=13746032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8142679A Pending JPS567130A (en) 1979-06-29 1979-06-29 Control system for input/output device

Country Status (1)

Country Link
JP (1) JPS567130A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5178956A (en) * 1974-12-30 1976-07-09 Fujitsu Ltd Kyoyofuairuno kyoseirizaabu reriizuhoshiki
JPS5199421A (en) * 1975-02-27 1976-09-02 Nippon Signal Co Ltd MARUCHIPUROSETSUSASHISUTEMUNIOKERU PUROSETSUSATANMATSUSOCHIKETSUGOSEIGYOHOSHIKI OYOBI SONOKAIRO
JPS5223235A (en) * 1975-08-18 1977-02-22 Nec Corp Input/output multiprocessor
JPS53119640A (en) * 1977-03-29 1978-10-19 Fujitsu Ltd Input-output control system capable of controlling cross-call

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5178956A (en) * 1974-12-30 1976-07-09 Fujitsu Ltd Kyoyofuairuno kyoseirizaabu reriizuhoshiki
JPS5199421A (en) * 1975-02-27 1976-09-02 Nippon Signal Co Ltd MARUCHIPUROSETSUSASHISUTEMUNIOKERU PUROSETSUSATANMATSUSOCHIKETSUGOSEIGYOHOSHIKI OYOBI SONOKAIRO
JPS5223235A (en) * 1975-08-18 1977-02-22 Nec Corp Input/output multiprocessor
JPS53119640A (en) * 1977-03-29 1978-10-19 Fujitsu Ltd Input-output control system capable of controlling cross-call

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