JPS57138253A - Direct reading system for circuit level - Google Patents
Direct reading system for circuit levelInfo
- Publication number
- JPS57138253A JPS57138253A JP2397681A JP2397681A JPS57138253A JP S57138253 A JPS57138253 A JP S57138253A JP 2397681 A JP2397681 A JP 2397681A JP 2397681 A JP2397681 A JP 2397681A JP S57138253 A JPS57138253 A JP S57138253A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- level
- domestic
- international
- meter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005259 measurement Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
- H04M3/26—Arrangements for supervision, monitoring or testing with means for applying test signals or for measuring
- H04M3/28—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor
- H04M3/32—Automatic routine testing ; Fault testing; Installation testing; Test methods, test equipment or test arrangements therefor for lines between exchanges
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Monitoring And Testing Of Exchanges (AREA)
Abstract
PURPOSE:To directly read the measured levels of international and domestic circuits, differing in level diagram, on a meter, by providing an international-side absolute-level switching circuit and a domestic-side absolute-level switching circuit, and their switching circuit and level meter. CONSTITUTION:For the level measurement of an international circuit 4, a monitor line 7 is inserted at the equipment position for the international circuit to be tested in a circuit bracketing device 6, and a value on a level meter 12 in a circuit test board 8 is read through an international-side absolute-level converting circuit 10, thus measuring the level of the international circuit. For the level measurement of a domestic circuit 5, the monitor line 7 is connected to the level meter 12 by a switching device 9 via a domestic-side absolute-level converting circuit 11 through keying operation on the console panel 13 of the circuit test board 8, and also inserted to the equipment position for the domestic circuit to be tested in the circuit bracketing device 6, thus directly reading the measured level of the domestic side on the level meter 12.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2397681A JPS57138253A (en) | 1981-02-20 | 1981-02-20 | Direct reading system for circuit level |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2397681A JPS57138253A (en) | 1981-02-20 | 1981-02-20 | Direct reading system for circuit level |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57138253A true JPS57138253A (en) | 1982-08-26 |
Family
ID=12125580
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2397681A Pending JPS57138253A (en) | 1981-02-20 | 1981-02-20 | Direct reading system for circuit level |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57138253A (en) |
-
1981
- 1981-02-20 JP JP2397681A patent/JPS57138253A/en active Pending
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