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JPS57117258A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57117258A
JPS57117258A JP56003370A JP337081A JPS57117258A JP S57117258 A JPS57117258 A JP S57117258A JP 56003370 A JP56003370 A JP 56003370A JP 337081 A JP337081 A JP 337081A JP S57117258 A JPS57117258 A JP S57117258A
Authority
JP
Japan
Prior art keywords
pad
periphery
protective film
thickness
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56003370A
Other languages
Japanese (ja)
Inventor
Kazuo Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Elemex Corp
Original Assignee
Ricoh Elemex Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Elemex Corp filed Critical Ricoh Elemex Corp
Priority to JP56003370A priority Critical patent/JPS57117258A/en
Publication of JPS57117258A publication Critical patent/JPS57117258A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To ensure a firm bonding of a semiconductor element and an outer circuit without exerting excessive pressure or adding heat to a semiconductor element, by making the surface of a protective film on a pad and the upper surface of the pad at the same level. CONSTITUTION:A periphery 10b of the upper surface 10 of a pad 10 is made into a step shape by etching. The thickness of a protective layer 12 is the same as the level difference of the periphery 10b of the pad 10 which makes the surface of the protective film 12 and the upper surface of the pad 10 at the same level. The level difference of the periphery 10b of the pad 10 is etched previously according to the thickness of the protective film 12.
JP56003370A 1981-01-13 1981-01-13 Semiconductor device Pending JPS57117258A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56003370A JPS57117258A (en) 1981-01-13 1981-01-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56003370A JPS57117258A (en) 1981-01-13 1981-01-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57117258A true JPS57117258A (en) 1982-07-21

Family

ID=11555455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56003370A Pending JPS57117258A (en) 1981-01-13 1981-01-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57117258A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6219741U (en) * 1985-07-20 1987-02-05

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6219741U (en) * 1985-07-20 1987-02-05

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