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JPS57113252A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57113252A
JPS57113252A JP55188115A JP18811580A JPS57113252A JP S57113252 A JPS57113252 A JP S57113252A JP 55188115 A JP55188115 A JP 55188115A JP 18811580 A JP18811580 A JP 18811580A JP S57113252 A JPS57113252 A JP S57113252A
Authority
JP
Japan
Prior art keywords
film
section
projection
oxidation
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55188115A
Other languages
Japanese (ja)
Inventor
Toshiaki Ogata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP55188115A priority Critical patent/JPS57113252A/en
Publication of JPS57113252A publication Critical patent/JPS57113252A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/7627—Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To decrease the difference of threshold voltage generated in the channel width direction by removing a projecting section of a single crystal silicon film through a selective oxidation method. CONSTITUTION:A porous oxide film 16 formed through the thermal oxidation of a porous silicon layer, the N type signle crystal silicon film 15 and a silicon nitride film 14 are shaped onto a P type silicon substrate 13. The projection 18 is formed naturally to the film 15 being insulated and isolated by the film 16 because of its manufacturing method. The film 15 is shaped, its surface is coated with an oxidation resisting substance while leaving an unnecessary section 27 containing the projecting section 18 of the film 15, and a gate wiring 24 is formed through selective oxidation, thus shaping the transistor, a channel section thereof has no projection.
JP55188115A 1980-12-29 1980-12-29 Manufacture of semiconductor device Pending JPS57113252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55188115A JPS57113252A (en) 1980-12-29 1980-12-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55188115A JPS57113252A (en) 1980-12-29 1980-12-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57113252A true JPS57113252A (en) 1982-07-14

Family

ID=16217961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55188115A Pending JPS57113252A (en) 1980-12-29 1980-12-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57113252A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6194367A (en) * 1984-10-16 1986-05-13 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and semiconductor device manufacturing method
US5103288A (en) * 1988-03-15 1992-04-07 Nec Corporation Semiconductor device having multilayered wiring structure with a small parasitic capacitance
US20130214374A1 (en) * 2010-06-30 2013-08-22 Canon Kabushiki Kaisha Semiconductor device, method of manufacturing the same, and solid-state image sensor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6194367A (en) * 1984-10-16 1986-05-13 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and semiconductor device manufacturing method
US5103288A (en) * 1988-03-15 1992-04-07 Nec Corporation Semiconductor device having multilayered wiring structure with a small parasitic capacitance
US20130214374A1 (en) * 2010-06-30 2013-08-22 Canon Kabushiki Kaisha Semiconductor device, method of manufacturing the same, and solid-state image sensor

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