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JPS57109368A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS57109368A
JPS57109368A JP55188804A JP18880480A JPS57109368A JP S57109368 A JPS57109368 A JP S57109368A JP 55188804 A JP55188804 A JP 55188804A JP 18880480 A JP18880480 A JP 18880480A JP S57109368 A JPS57109368 A JP S57109368A
Authority
JP
Japan
Prior art keywords
diffusion layer
junction
substrate
larger
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55188804A
Other languages
Japanese (ja)
Inventor
Haruyuki Hoshika
Takaaki Katou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55188804A priority Critical patent/JPS57109368A/en
Publication of JPS57109368A publication Critical patent/JPS57109368A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To increase junction capacitance without making any larger the plane area of an N<+> diffusion layer by forming a junction surface between the N<+> diffusion layer and a substrate uneven to make the junction area larger. CONSTITUTION:Depletion layers formed by the P-N junctions of the first poly- silicon layer 4 and an N<+> diffusion layer 8, and the diffusion layer 8 and a substrate 1, serve as capacitors. A junction surface 9 between the diffusion layer 8 and the substrate 1 right under the silicon layer 4 has an uneven surface. This increases the junction capacitance by making an overall junction area larger within the same plane area without interfering with minimizing the device.
JP55188804A 1980-12-25 1980-12-25 Semiconductor memory device Pending JPS57109368A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55188804A JPS57109368A (en) 1980-12-25 1980-12-25 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55188804A JPS57109368A (en) 1980-12-25 1980-12-25 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS57109368A true JPS57109368A (en) 1982-07-07

Family

ID=16230087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55188804A Pending JPS57109368A (en) 1980-12-25 1980-12-25 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS57109368A (en)

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