JPS57104248A - Manufacture of hybrid integrated circuit - Google Patents
Manufacture of hybrid integrated circuitInfo
- Publication number
- JPS57104248A JPS57104248A JP55180930A JP18093080A JPS57104248A JP S57104248 A JPS57104248 A JP S57104248A JP 55180930 A JP55180930 A JP 55180930A JP 18093080 A JP18093080 A JP 18093080A JP S57104248 A JPS57104248 A JP S57104248A
- Authority
- JP
- Japan
- Prior art keywords
- substrates
- spacers
- baked
- substrate
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 11
- 125000006850 spacer group Chemical group 0.000 abstract 5
- 239000003973 paint Substances 0.000 abstract 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 239000011889 copper foil Substances 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/80—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
- H10D86/85—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
PURPOSE:To prevent a warp generated in a substrate in a heating process by a method wherein a large number of the substrates and spacers are fast stuck and pressed and housed in a pressure jig while putting the spacers on one main surfaces of the substrates, the substrates and the spacers are heated together with the pressure jig, and resistance paints are baked. CONSTITUTION:A hybrid integrated circuit substrate is formed by a metal such as aluminum, and an insulating film is shaped through the anode oxidation, etc. of the surface and the surface is coated with the film. Copper foil is pasted onto the surfaces of the substrates and predetermined circuit patterns are formed through etching, and the resistance paints are screen-printed at prescribed positions and baked and resistors are shaped. When baking, however, the spacers 5, which contact with the fringes of the substrates 1 (dotted lines) and have vent slits 6, are contacted with the surfaces of the substrates, and the resistance paints are baked and the substrates are annealed under a condition that the spacers 5 and the substrates 1 are held alternately and pressed. Accordingly, a warp and torsion can be prevented even when the thickness of the substrate 1 is 1mm. or thinner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55180930A JPS5942460B2 (en) | 1980-12-19 | 1980-12-19 | Method for manufacturing hybrid integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55180930A JPS5942460B2 (en) | 1980-12-19 | 1980-12-19 | Method for manufacturing hybrid integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57104248A true JPS57104248A (en) | 1982-06-29 |
| JPS5942460B2 JPS5942460B2 (en) | 1984-10-15 |
Family
ID=16091758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55180930A Expired JPS5942460B2 (en) | 1980-12-19 | 1980-12-19 | Method for manufacturing hybrid integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5942460B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5844200A (en) * | 1996-05-16 | 1998-12-01 | Sendex Medical, Inc. | Method for drilling subminiature through holes in a sensor substrate with a laser |
-
1980
- 1980-12-19 JP JP55180930A patent/JPS5942460B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5844200A (en) * | 1996-05-16 | 1998-12-01 | Sendex Medical, Inc. | Method for drilling subminiature through holes in a sensor substrate with a laser |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5942460B2 (en) | 1984-10-15 |
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