JPS57103115A - Control circuit of magnetic recorder and reproducer - Google Patents
Control circuit of magnetic recorder and reproducerInfo
- Publication number
- JPS57103115A JPS57103115A JP17978280A JP17978280A JPS57103115A JP S57103115 A JPS57103115 A JP S57103115A JP 17978280 A JP17978280 A JP 17978280A JP 17978280 A JP17978280 A JP 17978280A JP S57103115 A JPS57103115 A JP S57103115A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- preset
- magnetic recorder
- inputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
PURPOSE:To eliminate a readout error due to variation in phase relation by reducing the variation of the pulse width of a data window signal with the phase variation of a readout pulse signal, by adding a preset data selecting circuit to a counter circuit. CONSTITUTION:A readout pulse signal, when inputted from a magnetic recorder 7 to a preset signal generating circuit 8, is converted into a preset signal. After preset data selected by a preset data selecting circuit 13 by the said signal is set in a counter circuit 9, the circuit 9 starts counting by a reference clock signal generated by a clock signal generating circuit 10. When the readout pulse signal is not inputted from the magnetic recorder 7 to the circuit 8, the circuit 9 continues counting operation by the reference clock signal. The output signal of the circuit 9 is inputted to a data window generating circuit 11, which generates a data window signal with necessary pulse width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17978280A JPS57103115A (en) | 1980-12-18 | 1980-12-18 | Control circuit of magnetic recorder and reproducer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17978280A JPS57103115A (en) | 1980-12-18 | 1980-12-18 | Control circuit of magnetic recorder and reproducer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57103115A true JPS57103115A (en) | 1982-06-26 |
Family
ID=16071791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17978280A Pending JPS57103115A (en) | 1980-12-18 | 1980-12-18 | Control circuit of magnetic recorder and reproducer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57103115A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54151014A (en) * | 1978-05-19 | 1979-11-27 | Oki Electric Ind Co Ltd | Demodulating system |
-
1980
- 1980-12-18 JP JP17978280A patent/JPS57103115A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54151014A (en) * | 1978-05-19 | 1979-11-27 | Oki Electric Ind Co Ltd | Demodulating system |
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