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JPS57100531A - Optical bus module - Google Patents

Optical bus module

Info

Publication number
JPS57100531A
JPS57100531A JP55177754A JP17775480A JPS57100531A JP S57100531 A JPS57100531 A JP S57100531A JP 55177754 A JP55177754 A JP 55177754A JP 17775480 A JP17775480 A JP 17775480A JP S57100531 A JPS57100531 A JP S57100531A
Authority
JP
Japan
Prior art keywords
signal
circuit
optical
register
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55177754A
Other languages
Japanese (ja)
Inventor
Kazuo Mikami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP55177754A priority Critical patent/JPS57100531A/en
Publication of JPS57100531A publication Critical patent/JPS57100531A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optical Communication System (AREA)

Abstract

PURPOSE:To convert a signal into an optical level and to transmit it to all other CPUs, by providing a own transmission control function and producing the transmission timing and a control signal regardless of the external signals. CONSTITUTION:When a CPU writes data into a local memory, a coincidence circuit 32 and then signals R/W-1 and DBE-1 plus clock signals E-1 and Q-1 are made active respectively to carry out the rising of a signal A of an address circuit 34 and the presetting of a shift register 31. At the same time, the register 31 is turned active via a D-flip-flop circuit 35 and a timer circuit 39. Thus a transmission oscillating circuit 38 makes a counter 37 advance via a gate 36, and a clock signal B is applied to the register 37. The signal B is then converted into an optical data signal of wavelength lambda1 and an optical clock signal of wavelength lambda2 by light emission driving circuits 41 and 42 plus lambda1 and lambda2 light emitting chips 44 and 45 to be transferred to another CPU via an optical fiber 48.
JP55177754A 1980-12-15 1980-12-15 Optical bus module Pending JPS57100531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55177754A JPS57100531A (en) 1980-12-15 1980-12-15 Optical bus module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55177754A JPS57100531A (en) 1980-12-15 1980-12-15 Optical bus module

Publications (1)

Publication Number Publication Date
JPS57100531A true JPS57100531A (en) 1982-06-22

Family

ID=16036534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55177754A Pending JPS57100531A (en) 1980-12-15 1980-12-15 Optical bus module

Country Status (1)

Country Link
JP (1) JPS57100531A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985005706A1 (en) * 1984-05-29 1985-12-19 Fanuc Ltd Signal input and picture display system
JPH01173214A (en) * 1987-12-24 1989-07-07 American Teleph & Telegr Co <Att> Optical back plane

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985005706A1 (en) * 1984-05-29 1985-12-19 Fanuc Ltd Signal input and picture display system
JPH01173214A (en) * 1987-12-24 1989-07-07 American Teleph & Telegr Co <Att> Optical back plane
JPH0577088B2 (en) * 1987-12-24 1993-10-26 American Telephone & Telegraph

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