JPS5691535A - Multiple-valued level output circuit - Google Patents
Multiple-valued level output circuitInfo
- Publication number
- JPS5691535A JPS5691535A JP16975579A JP16975579A JPS5691535A JP S5691535 A JPS5691535 A JP S5691535A JP 16975579 A JP16975579 A JP 16975579A JP 16975579 A JP16975579 A JP 16975579A JP S5691535 A JPS5691535 A JP S5691535A
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- output circuit
- inverters
- level output
- mos transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09425—Multistate logic
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To prevent a latch-up state and the destruction of an element by providing switching means between a couple of inverters differing in power voltage and a power source and by exercising complementary control over those switching means. CONSTITUTION:When a control signal is at level [L], MOS transistors T1 and T4 are on and MOS transistors T5 and T8 are off, enabling inverters of transistors T2 and T3 to operate with outputs at VSS1 and VDD1. When the control signal is at level [H], MOS transistors T1 and T4 are on and T5 and T8 are off, enabling inverters of transistors T2 and T3 to operate with outputs at VSS2 and VDD2.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16975579A JPS5691535A (en) | 1979-12-26 | 1979-12-26 | Multiple-valued level output circuit |
US06/216,818 US4408135A (en) | 1979-12-26 | 1980-12-16 | Multi-level signal generating circuit |
EP80108142A EP0031582A1 (en) | 1979-12-26 | 1980-12-22 | Multi-level signal generating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16975579A JPS5691535A (en) | 1979-12-26 | 1979-12-26 | Multiple-valued level output circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5691535A true JPS5691535A (en) | 1981-07-24 |
Family
ID=15892239
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16975579A Pending JPS5691535A (en) | 1979-12-26 | 1979-12-26 | Multiple-valued level output circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5691535A (en) |
-
1979
- 1979-12-26 JP JP16975579A patent/JPS5691535A/en active Pending
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