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JPS5674743A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS5674743A
JPS5674743A JP15098679A JP15098679A JPS5674743A JP S5674743 A JPS5674743 A JP S5674743A JP 15098679 A JP15098679 A JP 15098679A JP 15098679 A JP15098679 A JP 15098679A JP S5674743 A JPS5674743 A JP S5674743A
Authority
JP
Japan
Prior art keywords
data
register
memory
address
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15098679A
Other languages
Japanese (ja)
Inventor
Kinichi Takeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15098679A priority Critical patent/JPS5674743A/en
Publication of JPS5674743A publication Critical patent/JPS5674743A/en
Pending legal-status Critical Current

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  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE: To remarkably decrease the number of times for accessing a data and improve the efficiency for transmitting a data, by regenerating a compressed data by means of hardware, in the data processing system for regenerating a compressed data.
CONSTITUTION: The highest rank address of a compressed record in the memory 8 is set to the memory address register 10, and a flag data of the first record is read out into the memory data register 11. The number of bits contained in this flag data is counted, it is subtracted from the address value which has been set to the register 10, and it is set to the register 10. Whenever 1 bit each is output, shifting from the record buffer register 16 and the register 14 for storing a flag data, it is compared, a data showing coincidence is selected, and it is output as a regenerative data to the channel interface 17. In case of showing inconsistency, a data of the address of the memory 8 designated by the memory address register 10 is read out, and it is output as a regenerative data.
COPYRIGHT: (C)1981,JPO&Japio
JP15098679A 1979-11-21 1979-11-21 Data processing system Pending JPS5674743A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15098679A JPS5674743A (en) 1979-11-21 1979-11-21 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15098679A JPS5674743A (en) 1979-11-21 1979-11-21 Data processing system

Publications (1)

Publication Number Publication Date
JPS5674743A true JPS5674743A (en) 1981-06-20

Family

ID=15508779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15098679A Pending JPS5674743A (en) 1979-11-21 1979-11-21 Data processing system

Country Status (1)

Country Link
JP (1) JPS5674743A (en)

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