JPS5731062A - Log information store system - Google Patents
Log information store systemInfo
- Publication number
- JPS5731062A JPS5731062A JP10591280A JP10591280A JPS5731062A JP S5731062 A JPS5731062 A JP S5731062A JP 10591280 A JP10591280 A JP 10591280A JP 10591280 A JP10591280 A JP 10591280A JP S5731062 A JPS5731062 A JP S5731062A
- Authority
- JP
- Japan
- Prior art keywords
- data
- log information
- register
- block
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To store the contents of a register without increasing the number of memories for log information, by separating a data by a block selector signal at a 1/2 period of a machine cycle, and storing and recording said data in the log information memory. CONSTITUTION:A high krank data A1 part and a low rank data A2 part of a data register 1 are inputted to a selecting circuit 5, respectively, and outputs which have been selected by the circuit are inputted to a blolck 2-1 and 2-2 of a memory 2. On the other hand, the highest rank bit 3-0 of an address register 3 is bit-inverted by an inverting circuit 7 at a 1/2 machine cycle, and this highest rank bit 3-0 is supplied to the selecting circuit 5 and 6 by a block selector signal 4-1 and 4-2, respectively. Moreover, 3-1-3-7 bits of the register 3 are connected to the blocks 2-1, 2-2 of the memory 2, and are recorded to the block 2-1 if the signal 4-2 is ''0'', and to the block 2-1 if it is ''1'', by a write signal 9.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10591280A JPS5731062A (en) | 1980-07-31 | 1980-07-31 | Log information store system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10591280A JPS5731062A (en) | 1980-07-31 | 1980-07-31 | Log information store system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5731062A true JPS5731062A (en) | 1982-02-19 |
Family
ID=14420068
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10591280A Pending JPS5731062A (en) | 1980-07-31 | 1980-07-31 | Log information store system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5731062A (en) |
-
1980
- 1980-07-31 JP JP10591280A patent/JPS5731062A/en active Pending
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