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JPS5674680A - Zero reset second hand display system electronic clock - Google Patents

Zero reset second hand display system electronic clock

Info

Publication number
JPS5674680A
JPS5674680A JP15270879A JP15270879A JPS5674680A JP S5674680 A JPS5674680 A JP S5674680A JP 15270879 A JP15270879 A JP 15270879A JP 15270879 A JP15270879 A JP 15270879A JP S5674680 A JPS5674680 A JP S5674680A
Authority
JP
Japan
Prior art keywords
counter
reset
pulse motor
display system
hand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15270879A
Other languages
Japanese (ja)
Inventor
Terubumi Oshitari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP15270879A priority Critical patent/JPS5674680A/en
Publication of JPS5674680A publication Critical patent/JPS5674680A/en
Pending legal-status Critical Current

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  • Electromechanical Clocks (AREA)

Abstract

PURPOSE: To clearly display that a clock is operating, by stopping the second hand at that position unitl the time is set, and also raising an alarm sound, when the second has been reset to zero in a state that the time is advancing.
CONSTITUTION: When the second hand 21a is less than 30 seconds, the information of the second counter 8 is preset to the up-down counter with preset 10 by operating the second zero reset switch 20, and subsequently, the second counter 8 is reset. Also, in this case, the FF18 becomes a set state, and the AND gate is made OFF, therefore operation of the pulse motor 7 is stopped. While the pulse motor 7 stops, the counter 10 executes the down-count by the time counting signal P3, and also drives the buzzer by sending this signal P3 to the buzzer driving circuit 16. And, when the count value of the counter 10 becomes "0", regular driving of the pulse motor 7 is executed over again.
COPYRIGHT: (C)1981,JPO&Japio
JP15270879A 1979-11-26 1979-11-26 Zero reset second hand display system electronic clock Pending JPS5674680A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15270879A JPS5674680A (en) 1979-11-26 1979-11-26 Zero reset second hand display system electronic clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15270879A JPS5674680A (en) 1979-11-26 1979-11-26 Zero reset second hand display system electronic clock

Publications (1)

Publication Number Publication Date
JPS5674680A true JPS5674680A (en) 1981-06-20

Family

ID=15546408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15270879A Pending JPS5674680A (en) 1979-11-26 1979-11-26 Zero reset second hand display system electronic clock

Country Status (1)

Country Link
JP (1) JPS5674680A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS629194U (en) * 1985-07-02 1987-01-20

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS629194U (en) * 1985-07-02 1987-01-20

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