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JPS5672750A - Memory device - Google Patents

Memory device

Info

Publication number
JPS5672750A
JPS5672750A JP14982679A JP14982679A JPS5672750A JP S5672750 A JPS5672750 A JP S5672750A JP 14982679 A JP14982679 A JP 14982679A JP 14982679 A JP14982679 A JP 14982679A JP S5672750 A JPS5672750 A JP S5672750A
Authority
JP
Japan
Prior art keywords
address
data
signal
order
order address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14982679A
Other languages
Japanese (ja)
Inventor
Hisao Nagata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14982679A priority Critical patent/JPS5672750A/en
Publication of JPS5672750A publication Critical patent/JPS5672750A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the processing speed of data without interchanging actually data appearing frequently during arithmetic, by making it possible to assign colum address information indirectly by a memory method which can read and write the information.
CONSTITUTION: One digit of a binary-coded decimal number is stored in memory unit 1' where it can be read from and written from one address and the high-order address signal 40' from address register 4' is supplied as the high-order address decoder signal 50' to the high-order address decoder 2' by way of address converter 5'. Further, the low-order address signal 41' from register 4' is supplied to the low- order address decoder 3' to make it possible to select data that corresponds to the address by decoders 2' and 3'. With regard to the data selected by memory device 1', its address is assigned by address decoder signal 50' and low-order address signal 41' stored in converter 5' indicated indirectly by address signal 40', so that processing speed of data will be increased without interchanging data.
COPYRIGHT: (C)1981,JPO&Japio
JP14982679A 1979-11-19 1979-11-19 Memory device Pending JPS5672750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14982679A JPS5672750A (en) 1979-11-19 1979-11-19 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14982679A JPS5672750A (en) 1979-11-19 1979-11-19 Memory device

Publications (1)

Publication Number Publication Date
JPS5672750A true JPS5672750A (en) 1981-06-17

Family

ID=15483525

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14982679A Pending JPS5672750A (en) 1979-11-19 1979-11-19 Memory device

Country Status (1)

Country Link
JP (1) JPS5672750A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4994239A (en) * 1972-10-03 1974-09-06
JPS52155938A (en) * 1976-06-21 1977-12-24 Fujitsu Ltd Artificial shift system for data
JPS5464935A (en) * 1977-11-01 1979-05-25 Nec Corp Transfer control device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4994239A (en) * 1972-10-03 1974-09-06
JPS52155938A (en) * 1976-06-21 1977-12-24 Fujitsu Ltd Artificial shift system for data
JPS5464935A (en) * 1977-11-01 1979-05-25 Nec Corp Transfer control device

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