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JPS5587356A - Memory circuit device - Google Patents

Memory circuit device

Info

Publication number
JPS5587356A
JPS5587356A JP16070678A JP16070678A JPS5587356A JP S5587356 A JPS5587356 A JP S5587356A JP 16070678 A JP16070678 A JP 16070678A JP 16070678 A JP16070678 A JP 16070678A JP S5587356 A JPS5587356 A JP S5587356A
Authority
JP
Japan
Prior art keywords
read out
time
address
data
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16070678A
Other languages
Japanese (ja)
Inventor
Sumitoshi Shirasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16070678A priority Critical patent/JPS5587356A/en
Publication of JPS5587356A publication Critical patent/JPS5587356A/en
Priority to US06/346,145 priority patent/US4450538A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

Abstract

PURPOSE:To reduce the cycle time via the device featuring the easy manufacture by providing plural units of the memory circuit and then giving the time division to the information read out of those memory circuits in parallel via the corresponding address register to then carry out the serial output. CONSTITUTION:When the address signals of different LSB bits are supplied twice and continuously in address decoder 4 during the reading cycle time, address registers 61 and 62 are controlled by control circuit 7. Thus the data are read out in overlap and parallel from RAM31 and 32 in accordance with the addresses stored in registers 61 and 62. These data read out receive the time division via data multiplexer 9 controlled by read selection signal RS given from circuit 7 to be delivered in series. Accordingly, two sets of RAM's are read out at one time during the 1-time reading period, and thus the reading cycle is reduced substantially down to 1/2.
JP16070678A 1978-12-23 1978-12-23 Memory circuit device Pending JPS5587356A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP16070678A JPS5587356A (en) 1978-12-23 1978-12-23 Memory circuit device
US06/346,145 US4450538A (en) 1978-12-23 1982-02-05 Address accessed memory device having parallel to serial conversion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16070678A JPS5587356A (en) 1978-12-23 1978-12-23 Memory circuit device

Publications (1)

Publication Number Publication Date
JPS5587356A true JPS5587356A (en) 1980-07-02

Family

ID=15720697

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16070678A Pending JPS5587356A (en) 1978-12-23 1978-12-23 Memory circuit device

Country Status (1)

Country Link
JP (1) JPS5587356A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63129451A (en) * 1986-11-19 1988-06-01 Matsushita Graphic Commun Syst Inc Memory control circuit
JPS63221491A (en) * 1987-03-11 1988-09-14 Victor Co Of Japan Ltd Image data output device
JPH01286056A (en) * 1988-05-13 1989-11-17 Toshiba Corp Interleave memory access device
JPH0582073U (en) * 1991-03-15 1993-11-05 スタンレー電気株式会社 Lead wire mounting structure
WO1998002886A3 (en) * 1996-07-17 1998-05-07 Edward C M Chang Memory with fast decoding

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4984539A (en) * 1972-12-20 1974-08-14
JPS5191636A (en) * 1974-10-08 1976-08-11 Adoresushiteiho deetaseiseiho ronrijunikenshutsuho randamuakusesukiokusochi oyobi sonokokujishingohatsuseikairo oyobi sensuzofukuki
JPS52124825A (en) * 1976-04-12 1977-10-20 Mitsubishi Electric Corp High performance memory circuit
JPS5314525A (en) * 1976-07-26 1978-02-09 Nec Corp Memory circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4984539A (en) * 1972-12-20 1974-08-14
JPS5191636A (en) * 1974-10-08 1976-08-11 Adoresushiteiho deetaseiseiho ronrijunikenshutsuho randamuakusesukiokusochi oyobi sonokokujishingohatsuseikairo oyobi sensuzofukuki
JPS52124825A (en) * 1976-04-12 1977-10-20 Mitsubishi Electric Corp High performance memory circuit
JPS5314525A (en) * 1976-07-26 1978-02-09 Nec Corp Memory circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63129451A (en) * 1986-11-19 1988-06-01 Matsushita Graphic Commun Syst Inc Memory control circuit
JPS63221491A (en) * 1987-03-11 1988-09-14 Victor Co Of Japan Ltd Image data output device
JPH01286056A (en) * 1988-05-13 1989-11-17 Toshiba Corp Interleave memory access device
JPH0582073U (en) * 1991-03-15 1993-11-05 スタンレー電気株式会社 Lead wire mounting structure
WO1998002886A3 (en) * 1996-07-17 1998-05-07 Edward C M Chang Memory with fast decoding

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