JPS567127A - Input/output channel - Google Patents
Input/output channelInfo
- Publication number
- JPS567127A JPS567127A JP8202179A JP8202179A JPS567127A JP S567127 A JPS567127 A JP S567127A JP 8202179 A JP8202179 A JP 8202179A JP 8202179 A JP8202179 A JP 8202179A JP S567127 A JPS567127 A JP S567127A
- Authority
- JP
- Japan
- Prior art keywords
- data
- signal
- sent
- input
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Hardware Redundancy (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE: To realize the simultaneous writing of the data into two output/input devices without reading the data double out of the main unit but by installing plural units of interfaces plus the means which sets and stores the working mode.
CONSTITUTION: FF41, 42 and 43 indicate the double-write mode, the slave mode and the lock mode each. When module M1 is under the slave mode, M1 takes the data on bus 51 into data buffer 32 via multiplexer 31 and by data delay signal 53 sent from M2 in case FF43 is set. Then if data request signal 12 is given from the input/output device through interface 3, the head data of buffer 32 is put on bus 11. And signal 12 is sent to M2 in the form of signal 22. On the contrary, signal 52 is sent from M2 based on the data request signal sent from the input/output device which is connected to M2. And when both signals 12 and 52 are "ON", data delay signal 13 is sent to the input/output device. Then when signal 12 becomes "ON" again, the data on bus 11 is switched to repeat the same action.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8202179A JPS567127A (en) | 1979-06-30 | 1979-06-30 | Input/output channel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8202179A JPS567127A (en) | 1979-06-30 | 1979-06-30 | Input/output channel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS567127A true JPS567127A (en) | 1981-01-24 |
Family
ID=13762862
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8202179A Pending JPS567127A (en) | 1979-06-30 | 1979-06-30 | Input/output channel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS567127A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58137054A (en) * | 1981-10-01 | 1983-08-15 | ストレイタス・コンピユ−タ・インコ−ポレイテツド | Highly reliable digital data processor |
-
1979
- 1979-06-30 JP JP8202179A patent/JPS567127A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58137054A (en) * | 1981-10-01 | 1983-08-15 | ストレイタス・コンピユ−タ・インコ−ポレイテツド | Highly reliable digital data processor |
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