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JPS5658234A - Manufacture of semiconductor integrated circuit - Google Patents

Manufacture of semiconductor integrated circuit

Info

Publication number
JPS5658234A
JPS5658234A JP13383679A JP13383679A JPS5658234A JP S5658234 A JPS5658234 A JP S5658234A JP 13383679 A JP13383679 A JP 13383679A JP 13383679 A JP13383679 A JP 13383679A JP S5658234 A JPS5658234 A JP S5658234A
Authority
JP
Japan
Prior art keywords
chip
wafer
manufacture
integrated circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13383679A
Other languages
Japanese (ja)
Inventor
Koichi Oguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP13383679A priority Critical patent/JPS5658234A/en
Publication of JPS5658234A publication Critical patent/JPS5658234A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To increase efficiency of utilization of a wafer by a method wherein an IC chip having a larger area is provided in the center of an Si single crystal wafer and at the same time a small-chip-sized IC is formed on the peripheral section of the IC chip. CONSTITUTION:Using a mask whereon an IC pattern 9 with a large chip size is arranged in the cente of a glass substrate 8 and an IC pattern 10 with a small chip size is arranged on the surrounding region, IC patterns 6 and 7 having a different chip size are formed on an Si substrate 5 simultaneously. With this constitution, a wafer is utilized effectively and the cost of the chips can be cut down.
JP13383679A 1979-10-17 1979-10-17 Manufacture of semiconductor integrated circuit Pending JPS5658234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13383679A JPS5658234A (en) 1979-10-17 1979-10-17 Manufacture of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13383679A JPS5658234A (en) 1979-10-17 1979-10-17 Manufacture of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5658234A true JPS5658234A (en) 1981-05-21

Family

ID=15114169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13383679A Pending JPS5658234A (en) 1979-10-17 1979-10-17 Manufacture of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5658234A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5329157A (en) * 1992-07-17 1994-07-12 Lsi Logic Corporation Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area
EP0709740A1 (en) * 1994-09-30 1996-05-01 Texas Instruments Incorporated Integrated circuit and method of making the same
US5532934A (en) * 1992-07-17 1996-07-02 Lsi Logic Corporation Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions
US5561086A (en) * 1993-06-18 1996-10-01 Lsi Logic Corporation Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches
KR100807587B1 (en) * 2002-03-09 2008-02-28 엘지.필립스 엘시디 주식회사 Cutting method of liquid crystal panel

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5329157A (en) * 1992-07-17 1994-07-12 Lsi Logic Corporation Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area
US5340772A (en) * 1992-07-17 1994-08-23 Lsi Logic Corporation Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die
US5341024A (en) * 1992-07-17 1994-08-23 Lsi Logic Corporation Method of increasing the layout efficiency of dies on a wafer, and increasing the ratio of I/O area to active area per die
US5532934A (en) * 1992-07-17 1996-07-02 Lsi Logic Corporation Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions
US5561086A (en) * 1993-06-18 1996-10-01 Lsi Logic Corporation Techniques for mounting semiconductor dies in die-receiving areas having support structure having notches
EP0709740A1 (en) * 1994-09-30 1996-05-01 Texas Instruments Incorporated Integrated circuit and method of making the same
KR100807587B1 (en) * 2002-03-09 2008-02-28 엘지.필립스 엘시디 주식회사 Cutting method of liquid crystal panel

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