JPS5658192A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS5658192A JPS5658192A JP13132979A JP13132979A JPS5658192A JP S5658192 A JPS5658192 A JP S5658192A JP 13132979 A JP13132979 A JP 13132979A JP 13132979 A JP13132979 A JP 13132979A JP S5658192 A JPS5658192 A JP S5658192A
- Authority
- JP
- Japan
- Prior art keywords
- unbalance
- sense amplifier
- lines
- state
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To increase the sensitivity of a sense amplifier for the semiconductor memory device using the sense amplifier consisting of the flip-flop circuit, by detecting and storing the unbalanced state of a pair of inverters forming the sense amplifier and then compensating the unbalance in accordance with the storage. CONSTITUTION:The dynamic RAM actuates the sense amplifier 1 by setting the word line and the clock phi1 to ''0'' and the clock phi2 to ''1'' each at the end of the initialization. The amplifier 1 senses either one of the digit lines 20 and 21 as ''1'' and the other as ''0'' respectively according to the unbalance of the electric characteristics of the system. After this, the clocks phi1 and phi2 are set at ''1'' and ''0'' each, and the unbalance state of the lines 20 and 21 is stored in the static memory cell 31. According to the state of storage, the capacities 34 and 35 are added to the lines 20 and 21 with the degree of unbalance set to the 1/2 capacity value in a conversion of the digit line capacity. As a result, the unbalance of voltage can be dissolved to increase the sensitivity.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54131329A JPS6051197B2 (en) | 1979-10-13 | 1979-10-13 | semiconductor storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54131329A JPS6051197B2 (en) | 1979-10-13 | 1979-10-13 | semiconductor storage device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5658192A true JPS5658192A (en) | 1981-05-21 |
JPS6051197B2 JPS6051197B2 (en) | 1985-11-12 |
Family
ID=15055394
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54131329A Expired JPS6051197B2 (en) | 1979-10-13 | 1979-10-13 | semiconductor storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6051197B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58102389A (en) * | 1981-12-12 | 1983-06-17 | Nippon Telegr & Teleph Corp <Ntt> | Storage circuit |
JPS58121194A (en) * | 1982-01-11 | 1983-07-19 | Nippon Telegr & Teleph Corp <Ntt> | Memory circuit |
-
1979
- 1979-10-13 JP JP54131329A patent/JPS6051197B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58102389A (en) * | 1981-12-12 | 1983-06-17 | Nippon Telegr & Teleph Corp <Ntt> | Storage circuit |
JPS58121194A (en) * | 1982-01-11 | 1983-07-19 | Nippon Telegr & Teleph Corp <Ntt> | Memory circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS6051197B2 (en) | 1985-11-12 |
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