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JPS5652429A - Interface circuit of input/output device - Google Patents

Interface circuit of input/output device

Info

Publication number
JPS5652429A
JPS5652429A JP12788379A JP12788379A JPS5652429A JP S5652429 A JPS5652429 A JP S5652429A JP 12788379 A JP12788379 A JP 12788379A JP 12788379 A JP12788379 A JP 12788379A JP S5652429 A JPS5652429 A JP S5652429A
Authority
JP
Japan
Prior art keywords
signal
counter
sent back
sequence
interface circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12788379A
Other languages
Japanese (ja)
Inventor
Yoshio Yoshiura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12788379A priority Critical patent/JPS5652429A/en
Publication of JPS5652429A publication Critical patent/JPS5652429A/en
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To make it possible to exactly execute the refresh RF operation of a memory, by providing a refresh counter which outputs an overflow signal when a fixed number of clocks has been counted in the central control unit CC.
CONSTITUTION: In the I/O interface circuit which sends and receives the information by executing in order each sequence of wake-up, transfer and end between the central control unit CC and I/O, a response signal informing that I/O has received a control signal from CC to I/O is sent back by one signal line. Whenever a control signal 300 is sent, CC resets the RF counter 601 through the OR gate 600 and the first transition differentiating circuit 612. In case a response signal 301 from I/O is not sent back, when the counter 601 counts a fixed number of clocks CP, an overflow signal 605 is output, the flip-flop 609 is set, an IO mode signal 604 is sent back artificially, and the sequence is made to proceed. In this case, an RF signal 610 is output through the gate 611 by giving an instruction 615 to the following sequence.
COPYRIGHT: (C)1981,JPO&Japio
JP12788379A 1979-10-05 1979-10-05 Interface circuit of input/output device Pending JPS5652429A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12788379A JPS5652429A (en) 1979-10-05 1979-10-05 Interface circuit of input/output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12788379A JPS5652429A (en) 1979-10-05 1979-10-05 Interface circuit of input/output device

Publications (1)

Publication Number Publication Date
JPS5652429A true JPS5652429A (en) 1981-05-11

Family

ID=14970999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12788379A Pending JPS5652429A (en) 1979-10-05 1979-10-05 Interface circuit of input/output device

Country Status (1)

Country Link
JP (1) JPS5652429A (en)

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