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JPS5632824A - Pulse eliminating circuit - Google Patents

Pulse eliminating circuit

Info

Publication number
JPS5632824A
JPS5632824A JP10836379A JP10836379A JPS5632824A JP S5632824 A JPS5632824 A JP S5632824A JP 10836379 A JP10836379 A JP 10836379A JP 10836379 A JP10836379 A JP 10836379A JP S5632824 A JPS5632824 A JP S5632824A
Authority
JP
Japan
Prior art keywords
circuit
seconds
delay
input signal
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10836379A
Other languages
Japanese (ja)
Inventor
Takao Tosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10836379A priority Critical patent/JPS5632824A/en
Publication of JPS5632824A publication Critical patent/JPS5632824A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To eliminate a spike-shaped pulse by a simple circuit by performing AND operation between an original input signal and a signal obtained by delaying the input signal by a certain time. CONSTITUTION:A signal inputted to input terminal (a) is partially supplied to AND circuit 6 and the remainder is inputted to AND circuit 6 by way of the delay circuit consisting of (n) inverters 51...5n. Assuming that each inverter has a delay time of (t) seconds, delay of (n)X(t) seconds is brought to effect. At the output of AND circuit 6, no input signal with a time lag exceeding (n)X(t) seconds appears, so that a spike-shaped pulse can easily be eliminated.
JP10836379A 1979-08-24 1979-08-24 Pulse eliminating circuit Pending JPS5632824A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10836379A JPS5632824A (en) 1979-08-24 1979-08-24 Pulse eliminating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10836379A JPS5632824A (en) 1979-08-24 1979-08-24 Pulse eliminating circuit

Publications (1)

Publication Number Publication Date
JPS5632824A true JPS5632824A (en) 1981-04-02

Family

ID=14482840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10836379A Pending JPS5632824A (en) 1979-08-24 1979-08-24 Pulse eliminating circuit

Country Status (1)

Country Link
JP (1) JPS5632824A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57168331U (en) * 1981-04-16 1982-10-23
EP0108702A2 (en) * 1982-11-01 1984-05-16 United Technologies Corporation Serial to parallel data conversion circuit
US4695145A (en) * 1985-02-07 1987-09-22 Canon Kabushiki Kaisha Motor built-in lens mounting
US5019724A (en) * 1989-12-20 1991-05-28 Sgs-Thomson Microelectronics, Inc. Noise tolerant input buffer
US5485112A (en) * 1988-12-21 1996-01-16 Texas Instruments Incorporated Metastable tolerant latach
US6392474B1 (en) 1999-09-07 2002-05-21 Bae Systems Information And Electronic Systems Integration Inc. Circuit for filtering single event effect (see) induced glitches

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5115362A (en) * 1974-07-29 1976-02-06 Tokyo Keiki Kk

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5115362A (en) * 1974-07-29 1976-02-06 Tokyo Keiki Kk

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57168331U (en) * 1981-04-16 1982-10-23
EP0108702A2 (en) * 1982-11-01 1984-05-16 United Technologies Corporation Serial to parallel data conversion circuit
US4695145A (en) * 1985-02-07 1987-09-22 Canon Kabushiki Kaisha Motor built-in lens mounting
US5485112A (en) * 1988-12-21 1996-01-16 Texas Instruments Incorporated Metastable tolerant latach
US5019724A (en) * 1989-12-20 1991-05-28 Sgs-Thomson Microelectronics, Inc. Noise tolerant input buffer
US6392474B1 (en) 1999-09-07 2002-05-21 Bae Systems Information And Electronic Systems Integration Inc. Circuit for filtering single event effect (see) induced glitches

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