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JPS5619260A - Digital variable multiplex converter - Google Patents

Digital variable multiplex converter

Info

Publication number
JPS5619260A
JPS5619260A JP9541279A JP9541279A JPS5619260A JP S5619260 A JPS5619260 A JP S5619260A JP 9541279 A JP9541279 A JP 9541279A JP 9541279 A JP9541279 A JP 9541279A JP S5619260 A JPS5619260 A JP S5619260A
Authority
JP
Japan
Prior art keywords
circuit
time slot
wire type
multiple signal
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9541279A
Other languages
Japanese (ja)
Other versions
JPS5834061B2 (en
Inventor
Tomoji Inoue
Hishiichi Komiya
Tatsuhiko Nishizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP54095412A priority Critical patent/JPS5834061B2/en
Publication of JPS5619260A publication Critical patent/JPS5619260A/en
Publication of JPS5834061B2 publication Critical patent/JPS5834061B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To perform the multiplexing, separation, line concentration and exchange each in the time-division way, by utilizing the temporary device for velocity conversion, designating the time address of the reading/writing of the memory device and also securing the change of the address designation. CONSTITUTION:The multiple signal supplied to multiple input terminal A1 is supplied in common to input terminal i3 (i=1-k) of each circuit. The circuit number showing which circuit the time slot within the frame is separated to from the input multiple signal is stored in writing address designating circuit A7. The information of circuit number is applied to writing address control circuit i9 of each circuit, and the time slot to be written into temporary memory device 16 is designated. The time slot is then read out in device i6 in the velocity and frame suited to the i-th 2-wire type transmission and then transmitted to 2-wire type line i1 through transmitter i5 and balance-unbalance converting transformer i2 each. Accordingly, the cange is possible for which 2-wire type transmission line the multiple signal is separated to by changing the contents of circuit A7.
JP54095412A 1979-07-25 1979-07-25 Digital variable multiplex converter Expired JPS5834061B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54095412A JPS5834061B2 (en) 1979-07-25 1979-07-25 Digital variable multiplex converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54095412A JPS5834061B2 (en) 1979-07-25 1979-07-25 Digital variable multiplex converter

Publications (2)

Publication Number Publication Date
JPS5619260A true JPS5619260A (en) 1981-02-23
JPS5834061B2 JPS5834061B2 (en) 1983-07-23

Family

ID=14136956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54095412A Expired JPS5834061B2 (en) 1979-07-25 1979-07-25 Digital variable multiplex converter

Country Status (1)

Country Link
JP (1) JPS5834061B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6139661A (en) * 1984-07-30 1986-02-25 Nec Corp Circuit editing device
JPH04506142A (en) * 1989-06-16 1992-10-22 ブリテイッシュ・テレコミュニケーションズ・パブリック・リミテッド・カンパニー data switching node

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6139661A (en) * 1984-07-30 1986-02-25 Nec Corp Circuit editing device
JPH04506142A (en) * 1989-06-16 1992-10-22 ブリテイッシュ・テレコミュニケーションズ・パブリック・リミテッド・カンパニー data switching node

Also Published As

Publication number Publication date
JPS5834061B2 (en) 1983-07-23

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